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https://bitbucket.org/smil3y/kde-workspace.git
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784 lines
24 KiB
C
784 lines
24 KiB
C
/* Retrive information about PCI subsystem through libpci library from
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pciutils package. This should be possible on Linux, BSD and AIX.
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Device classes, subclasses and programming interfaces are hardcoded
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here, since there are only few of them, and they are important and
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should their names be translated.
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pci.cpp private header, don't include in other files.
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Author: Konrad Rzepecki <hannibal@megapolis.pl>
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*/
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#ifndef KCONTROL_KPCI_PRIVATE_H
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#define KCONTROL_KPCI_PRIVATE_H
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#include "kpci.h"
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#include <QString>
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#include <klocale.h>
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//pci lookup buffer size
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#define NAME_BUFFER_SIZE 256
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//common used strings
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static const char strCtxt[]="state of PCI item";
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static const char strEnabled[]=I18N_NOOP2("state of PCI item", "Enabled");
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static const char strDisabled[]=I18N_NOOP2("state of PCI item", "Disabled");
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static const char strYes[]=I18N_NOOP2("state of PCI item", "Yes");
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static const char strNo[]=I18N_NOOP2("state of PCI item", "No");
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static const char strUnknown[]=I18N_NOOP2("state of PCI item", "Unknown");
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struct id2name {
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int id;
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QString name;
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};
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struct id3name {
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int id,id2;
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QString name;
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};
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struct id4name {
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int id,id2,id3;
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QString name;
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};
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union pciInfo {
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unsigned char raw[256];
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struct {
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unsigned short vendor;
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unsigned short device;
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union {
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unsigned short command;
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struct {
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unsigned comIo:1;
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unsigned comMemory:1;
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unsigned comMaster:1;
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unsigned comSpecial:1;
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unsigned comInvalidate:1;
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unsigned comVgaPalette:1;
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unsigned comParity:1;
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unsigned comWait:1;
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unsigned comSerr:1;
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unsigned comFastBack:1;
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unsigned comInterrupt:1;
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unsigned comUnk:5;
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} command_bits Q_PACKED;
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} command Q_PACKED;
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union {
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unsigned short status;
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struct {
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unsigned statUnk:3;
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unsigned statInterrupt:1;
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unsigned statCapList:1;
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unsigned stat66MHz:1;
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unsigned statUdf:1;
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unsigned statFastBack:1;
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unsigned statParity:1;
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unsigned statDevsel:2;
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unsigned statSigTargetAbort:1;
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unsigned statRecTargetAbort:1;
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unsigned statRecMasterAbort:1;
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unsigned statSigSystemError:1;
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unsigned statDetectedParity:1;
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} status_bits Q_PACKED;
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} status Q_PACKED;
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unsigned char revision;
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union {
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unsigned char devProgIface;
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struct {
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unsigned progPriOperMode:1;
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unsigned progPriProgInd:1;
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unsigned progSecOperMode:1;
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unsigned progSecProgInd:1;
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unsigned progUnk:3;
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unsigned progIdeMaster:1;
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} devProgIface_bits Q_PACKED;
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} devProgIface Q_PACKED;
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unsigned char devSubClass;
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unsigned char devClass;
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unsigned char cacheLineSize;
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unsigned char latencyTimer;
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union {
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unsigned char headerTypeFull:1;
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struct {
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unsigned headerType:7;
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unsigned multifunctional:1;
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} headerType_bits Q_PACKED;
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} headerType Q_PACKED;
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union {
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unsigned char bist;
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struct {
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unsigned bistCode:4;
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unsigned bistUnk:2;
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unsigned bistStart:1;
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unsigned bistCapable:1;
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} bist_bits Q_PACKED;
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} bist Q_PACKED;
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union {
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struct { //header0
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union {
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unsigned baseAddress;
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struct {
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unsigned baseAddressMap:1;
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unsigned baseAddressType:2;
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unsigned baseAddressPref:1;
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unsigned baseAddressAddr:28;
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} baseAddress_bits Q_PACKED;
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} Q_PACKED mapping[6];
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unsigned cardbusCis;
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unsigned short subVendor;
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unsigned short subDevice;
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union {
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unsigned romAddress;
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struct {
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unsigned romEnabled:1;
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unsigned romUnk:10;
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unsigned romAddr:21;
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} romAddress_bits Q_PACKED;
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} romAddress Q_PACKED;
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unsigned char capabilityList;
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unsigned char reserved1[7];
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unsigned char interruptLine;
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unsigned char interruptPin;
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unsigned char minGnt;
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unsigned char maxLat;
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} header0 Q_PACKED;
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struct { //header1
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unsigned baseAddress0_2;
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unsigned baseAddress1_2;
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unsigned char primaryBus;
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unsigned char secondaryBus;
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unsigned char subordinateBus;
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unsigned char secLatencyTimer;
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union {
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unsigned char ioBase;
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struct {
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unsigned ioBaseType:1;
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unsigned ioBaseUnk:3;
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unsigned ioBaseAddr:4;
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} ioBase_bits Q_PACKED;
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} ioBase Q_PACKED;
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unsigned char ioLimit;
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union {
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unsigned short secStatus;
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struct {
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unsigned secStatUnk:3;
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unsigned secStatInterrupt:1;
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unsigned secStatCapList:1;
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unsigned secStat66MHz:1;
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unsigned secStatUdf:1;
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unsigned secStatFastBack:1;
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unsigned secStatParity:1;
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unsigned secStatDevsel:2;
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unsigned secStatSigTargetAbort:1;
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unsigned secStatRecTargetAbort:1;
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unsigned secStatRecMasterAbort:1;
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unsigned secStatSigSystemError:1;
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unsigned secStatDetectedParity:1;
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} secStatus_bits Q_PACKED;
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} secStatus Q_PACKED;
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union {
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unsigned short memoryBase;
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struct {
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unsigned memoryType:1;
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unsigned memoryUnk:3;
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unsigned memoryAddr:4;
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} memoryBase_bits Q_PACKED;
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} memoryBase Q_PACKED;
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unsigned short memoryLimit;
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union {
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unsigned short prefMemoryBase;
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struct {
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unsigned prefMemoryType:1;
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unsigned prefMemoryUnk:3;
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unsigned prefMemoryAddr:4;
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} prefMemoryBase_bits Q_PACKED;
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} prefMemoryBase Q_PACKED;
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unsigned short prefMemoryLimit;
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unsigned prefBaseUpper32;
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unsigned prefLimitUpper32;
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unsigned short ioBaseUpper16;
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unsigned short ioLimitUpper16;
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unsigned char capabilityList_2;
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unsigned char reserved2[3];
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unsigned romAddress1;
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unsigned char interruptLine_2;
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unsigned char interruptPin_2;
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union {
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unsigned short bridgeControl;
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struct {
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unsigned bridgeControlParity:1;
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unsigned bridgeControlSerr:1;
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unsigned bridgeControlIsa:1;
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unsigned bridgeControlVga:1;
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unsigned bridgeControlUnk:1;
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unsigned bridgeControlMasterAbort:1;
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unsigned bridgeControlBusReset:1;
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unsigned bridgeControlFastBack:1;
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unsigned bridgeControlPriDisTim:1;
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unsigned bridgeControlSecDisTim:1;
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unsigned bridgeControlDisTimStat:1;
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unsigned bridgeControlDisTimeSerr:1;
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unsigned bridgeControlUnk2:4;
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} bridgeControl_bits Q_PACKED;
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} bridgeControl Q_PACKED;
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} header1 Q_PACKED;
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struct{ //header2
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unsigned baseAddress0_3;
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union {
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unsigned short cbSecStatus;
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struct {
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unsigned cbSecStatUnk:3;
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unsigned cbSecStatInterrupt:1;
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unsigned cbSecStatCapList:1;
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unsigned cbSecStat66MHz:1;
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unsigned cbSecStatUdf:1;
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unsigned cbSecStatFastBack:1;
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unsigned cbSecStatParity:1;
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unsigned cbSecStatDevsel:2;
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unsigned cbSecStatSigTargetAbort:1;
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unsigned cbSecStatRecTargetAbort:1;
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unsigned cbSecStatRecMasterAbort:1;
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unsigned cbSecStatSigSystemError:1;
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unsigned cbSecStatDetectedParity:1;
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} cbSecStatus_bits Q_PACKED;
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} cbSecStatus Q_PACKED;
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unsigned char cbPrimaryBus;
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unsigned char cbCardBus;
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unsigned char cbSubordinateBus;
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unsigned char cbLatencyTimer;
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struct {
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unsigned cbMemoryBase;
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unsigned cbMemoryLimit;
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} Q_PACKED cbMemory[2];
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struct {
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union {
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unsigned cbIoBase;
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struct {
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unsigned cbIoBaseType:1;
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unsigned coIoBaseUnk:1;
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unsigned cbIoBaseAddr:30;
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} cbIoBase_bits Q_PACKED;
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} cbIoBase Q_PACKED;
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unsigned cbIoLimit;
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} Q_PACKED cbIo[2];
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unsigned char interruptLine_3;
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unsigned char interruptPin_3;
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union {
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unsigned short cbControl;
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struct {
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unsigned cbControlParity:1;
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unsigned cbControlSerr:1;
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unsigned cbControlIsa:1;
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unsigned cbControlVga:1;
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unsigned cbControlUnk:1;
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unsigned cbControlMasterAbort:1;
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unsigned cbControlBusReset:1;
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unsigned cbControl16Int:1;
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unsigned cbControlPref0:1;
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unsigned cbControlPref1:1;
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unsigned cbControlPostWrites:1;
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unsigned cbControlUnk2:5;
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} cbControl_bits Q_PACKED;
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} cbControl Q_PACKED;
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unsigned short cbSubVendor;
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unsigned short cbSubDevice;
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unsigned short cbLegacyModeBase;
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} header2 Q_PACKED;
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} header Q_PACKED;
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} cooked Q_PACKED;
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} Q_PACKED;
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union agpInfo{
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unsigned char raw[10];
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struct {
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struct {
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unsigned revMinor:4;
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unsigned revMaior:4;
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unsigned char unk;
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} revision Q_PACKED;
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union {
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unsigned status;
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struct {
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unsigned statusEnhRate:4;
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unsigned statusUnk:28;
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} status_bits0 Q_PACKED;
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struct {
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unsigned statusRate:3;
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unsigned statusMode:1;
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unsigned statusFastWrite:1;
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unsigned statusOver4gb:1;
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unsigned statusHtrans:1;
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unsigned statusGart64b:1;
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unsigned statusItaCoh:1;
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unsigned statusSba:1;
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unsigned statusCalCycle:3;
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unsigned statusOptReqSize:3;
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unsigned statusUnk1:1;
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unsigned statusIsochSupp:1;
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unsigned statusUnk2:6;
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unsigned statusReq:8;
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} status_bits1 Q_PACKED;
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} status Q_PACKED;
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union {
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unsigned config;
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struct {
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unsigned configEnhRate:4;
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unsigned configUnk:28;
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} config_bits0 Q_PACKED;
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struct {
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unsigned configRate:3;
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unsigned configUnk1:1;
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unsigned configFastWrite:1;
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unsigned configOver4gb:1;
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unsigned configUnk2:1;
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unsigned configGart64b:1;
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unsigned configAgp:1;
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unsigned configSba:1;
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unsigned configCalCycle:3;
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unsigned configOptReqSize:3;
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unsigned configUnk3:8;
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unsigned configReq:8;
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} config_bits1 Q_PACKED;
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} config Q_PACKED;
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} cooked Q_PACKED;
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} Q_PACKED;
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union pmInfo {
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unsigned char raw[6];
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struct {
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union {
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unsigned short caps;
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struct {
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unsigned capsVer:3;
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unsigned capsClock:1;
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unsigned capsUnk:1;
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unsigned capsDsi:1;
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unsigned capsAuxCur:3;
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unsigned capsD1Supp:1;
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unsigned capsD2Supp:1;
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unsigned capsPmeD0:1;
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unsigned capsPmeD1:1;
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unsigned capsPmeD2:1;
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unsigned capsPmeD3hot:1;
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unsigned capsPmeD3cold:1;
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} caps_bits Q_PACKED;
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} caps Q_PACKED;
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union {
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unsigned short status;
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struct {
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unsigned statPower:2;
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unsigned statUnk:6;
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unsigned statPme:1;
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unsigned statDataSelect:4;
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unsigned statDataScale:2;
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unsigned statPmeStat:1;
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} status_bits Q_PACKED;
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} status Q_PACKED;
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union {
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unsigned char statusBridge;
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struct {
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unsigned statBridgeUnk:6;
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unsigned statBridgeBx:1;
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unsigned statBridgeClock:1;
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} statusBridge_bits Q_PACKED;
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} statusBridge Q_PACKED;
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unsigned char data;
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} cooked Q_PACKED;
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} Q_PACKED;
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union vpdInfo {
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unsigned char raw[6];
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struct {
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unsigned vpdAddress:15;
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unsigned vpdTransfer:1;
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unsigned vpdData;
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} cooked Q_PACKED;
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} Q_PACKED;
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union msiInfo {
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unsigned char raw[22];
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struct {
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union {
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unsigned short msiControl;
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struct {
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unsigned msiEnable:1;
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unsigned msiMmCapable:3;
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unsigned msiMmEnable:3;
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unsigned msi64bit:1;
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unsigned msiPerVector:1;
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unsigned msiUnk0:7;
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} msiControl_bits Q_PACKED;
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} msiControl Q_PACKED;
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unsigned msiAddress;
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union {
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struct {
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unsigned msiUpperAddress;
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unsigned short msiData64;
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unsigned short msiUnk64;
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unsigned msiMask64;
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unsigned msiPending64;
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} address Q_PACKED;
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struct {
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unsigned short msiData;
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unsigned short msiUnk;
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unsigned msiMask;
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unsigned msiPending;
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} data Q_PACKED;
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} payload Q_PACKED;
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} cooked Q_PACKED;
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} Q_PACKED;
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//In following arrays -1 mean default value
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//keep -1 in last position
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//device classes list
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static const id2name devClass[]={{ 0x00, i18n("Unclassified device")},
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{ 0x01, i18n("Mass storage controller")},
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{ 0x02, i18n("Network controller")},
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{ 0x03, i18n("Display controller")},
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{ 0x04, i18n("Multimedia controller")},
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{ 0x05, i18n("Memory controller")},
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{ 0x06, i18n("Bridge")},
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{ 0x07, i18n("Communication controller")},
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{ 0x08, i18n("Generic system peripheral")},
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{ 0x09, i18n("Input device controller")},
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{ 0x0A, i18n("Docking station")},
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{ 0x0B, i18n("Processor")},
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{ 0x0C, i18n("Serial bus controller")},
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{ 0x0D, i18n("Wireless controller")},
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{ 0x0E, i18n("Intelligent controller")},
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{ 0x0F, i18n("Satellite communications controller")},
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{ 0x10, i18n("Encryption controller")},
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{ 0x11, i18n("Signal processing controller")},
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{ -1, i18n("Unknown device class")}
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};
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//keep -1 in last position in "id"
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//and in last position in "id2" with certain "id"
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//subdevice classes list
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static const id3name devSubclass[]={ { 0x00, 0x00, i18n("Non-VGA unclassified device")},
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{ 0x00, 0x01, i18n("VGA unclassified device")},
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{ 0x00, -1, i18n("Unknown unclassified device")},
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{ 0x01, 0x00, i18n("SCSI storage controller")},
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{ 0x01, 0x01, i18n("IDE controller")},
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{ 0x01, 0x02, i18n("Floppy disk controller")},
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{ 0x01, 0x03, i18n("IPI bus controller")},
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{ 0x01, 0x04, i18n("RAID bus controller")},
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{ 0x01, 0x05, i18n("ATA controller")},
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{ 0x01, 0x06, i18n("Serial ATA direct port access")},
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{ 0x01, 0x80, i18n("Mass storage controller")},
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{ 0x01, -1, i18n("Unknown storage controller")},
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{ 0x02, 0x00, i18n("Ethernet controller")},
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{ 0x02, 0x01, i18n("Token ring network controller")},
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{ 0x02, 0x02, i18n("FDDI network controller")},
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{ 0x02, 0x03, i18n("ATM network controller")},
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{ 0x02, 0x04, i18n("ISDN controller")},
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{ 0x02, 0x05, i18n("WorldFip controller")},
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{ 0x02, 0x06, i18n("PICMG 2.14 multi computing")},
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{ 0x02, 0x80, i18n("Network controller")},
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{ 0x02, -1, i18n("Unknown network controller")},
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{ 0x03, 0x00, i18n("VGA compatible controller")},
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{ 0x03, 0x01, i18n("XGA compatible controller")},
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{ 0x03, 0x02, i18n("3D controller")},
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{ 0x03, 0x80, i18n("Display controller")},
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{ 0x03, -1, i18n("Unknown display controller")},
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{ 0x04, 0x00, i18n("Multimedia video controller")},
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{ 0x04, 0x01, i18n("Multimedia audio controller")},
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{ 0x04, 0x02, i18n("Computer telephony device")},
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{ 0x04, 0x80, i18n("Multimedia controller")},
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{ 0x04, -1, i18n("Unknown multimedia controller")},
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{ 0x05, 0x00, i18n("RAM memory")},
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{ 0x05, 0x01, i18n("FLASH memory")},
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{ 0x05, 0x80, i18n("Memory controller")},
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{ 0x05, -1, i18n("Unknown memory controller")},
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{ 0x06, 0x00, i18n("Host bridge")},
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{ 0x06, 0x01, i18n("ISA bridge")},
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{ 0x06, 0x02, i18n("EISA bridge")},
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{ 0x06, 0x03, i18n("MicroChannel bridge")},
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{ 0x06, 0x04, i18n("PCI bridge")},
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{ 0x06, 0x05, i18n("PCMCIA bridge")},
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{ 0x06, 0x06, i18n("NuBus bridge")},
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{ 0x06, 0x07, i18n("CardBus bridge")},
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{ 0x06, 0x08, i18n("RACEway bridge")},
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{ 0x06, 0x09, i18n("Semi-transparent PCI-to-PCI bridge")},
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{ 0x06, 0x0A, i18n("InfiniBand to PCI host bridge")},
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{ 0x06, 0x80, i18n("Bridge")},
|
|
{ 0x06, -1, i18n("Unknown bridge")},
|
|
|
|
{ 0x07, 0x00, i18n("Serial controller")},
|
|
{ 0x07, 0x01, i18n("Parallel controller")},
|
|
{ 0x07, 0x02, i18n("Multiport serial controller")},
|
|
{ 0x07, 0x03, i18n("Modem")},
|
|
{ 0x07, 0x04, i18n("GPIB (IEEE 488.1/2) controller")},
|
|
{ 0x07, 0x05, i18n("Smart card")},
|
|
{ 0x07, 0x80, i18n("Communication controller")},
|
|
{ 0x07, -1, i18n("Unknown communication controller")},
|
|
|
|
{ 0x08, 0x00, i18n("PIC")},
|
|
{ 0x08, 0x01, i18n("DMA controller")},
|
|
{ 0x08, 0x02, i18n("Timer")},
|
|
{ 0x08, 0x03, i18n("RTC")},
|
|
{ 0x08, 0x04, i18n("PCI Hot-plug controller")},
|
|
{ 0x08, 0x80, i18n("System peripheral")},
|
|
{ 0x08, -1, i18n("Unknown system peripheral")},
|
|
|
|
{ 0x09, 0x00, i18n("Keyboard controller")},
|
|
{ 0x09, 0x01, i18n("Digitizer Pen")},
|
|
{ 0x09, 0x02, i18n("Mouse controller")},
|
|
{ 0x09, 0x03, i18n("Scanner controller")},
|
|
{ 0x09, 0x04, i18n("Gameport controller")},
|
|
{ 0x09, 0x80, i18n("Input device controller")},
|
|
{ 0x09, -1, i18n("Unknown input device controller")},
|
|
|
|
{ 0x0A, 0x00, i18n("Generic docking station")},
|
|
{ 0x0A, 0x80, i18n("Docking station")},
|
|
{ 0x0A, -1, i18n("Unknown docking station")},
|
|
|
|
{ 0x0B, 0x00, i18n("386")},
|
|
{ 0x0B, 0x01, i18n("486")},
|
|
{ 0x0B, 0x02, i18n("Pentium")},
|
|
{ 0x0B, 0x10, i18n("Alpha")},
|
|
{ 0x0B, 0x20, i18n("Power PC")},
|
|
{ 0x0B, 0x30, i18n("MIPS")},
|
|
{ 0x0B, 0x40, i18n("Co-processor")},
|
|
{ 0x0B, -1, i18n("Unknown processor")},
|
|
|
|
{ 0x0C, 0x00, i18n("FireWire (IEEE 1394)")},
|
|
{ 0x0C, 0x01, i18n("ACCESS bus")},
|
|
{ 0x0C, 0x02, i18n("SSA")},
|
|
{ 0x0C, 0x03, i18n("USB controller")},
|
|
{ 0x0C, 0x04, i18n("Fibre channel")},
|
|
{ 0x0C, 0x05, i18n("SMBus")},
|
|
{ 0x0C, 0x06, i18n("InfiniBand")},
|
|
{ 0x0C, 0x07, i18n("IPMI interface")},
|
|
{ 0x0C, 0x08, i18n("SERCOS interface")},
|
|
{ 0x0C, 0x09, i18n("CANbus")},
|
|
{ 0x0C, -1, i18n("Unknown serial bus controller")},
|
|
|
|
{ 0x0D, 0x00, i18n("IRDA controller")},
|
|
{ 0x0D, 0x01, i18n("Consumer IR controller")},
|
|
{ 0x0D, 0x10, i18n("RF controller")},
|
|
{ 0x0D, 0x11, i18n("Bluetooth")},
|
|
{ 0x0D, 0x12, i18n("Broadband")},
|
|
{ 0x0D, 0x20, i18n("Ethernet (802.11a - 5 GHz)")},
|
|
{ 0x0D, 0x21, i18n("Ethernet (802.11b - 2.4 GHz)")},
|
|
{ 0x0D, 0x80, i18n("Wireless controller")},
|
|
{ 0x0D, -1, i18n("Unknown wireless controller")},
|
|
|
|
{ 0x0E, 0x00, i18n("I2O")},
|
|
{ 0x0E, -1, i18n("Unknown intelligent controller")},
|
|
|
|
{ 0x0F, 0x01, i18n("Satellite TV controller")},
|
|
{ 0x0F, 0x02, i18n("Satellite audio communication controller")},
|
|
{ 0x0F, 0x03, i18n("Satellite voice communication controller")},
|
|
{ 0x0F, 0x04, i18n("Satellite data communication controller")},
|
|
{ 0x0F, -1, i18n("Unknown satellite communications controller")},
|
|
|
|
{ 0x10, 0x00, i18n("Network and computing encryption device")},
|
|
{ 0x10, 0x10, i18n("Entertainment encryption device")},
|
|
{ 0x10, 0x80, i18n("Encryption controller")},
|
|
{ 0x10, -1, i18n("Unknown encryption controller")},
|
|
|
|
{ 0x11, 0x00, i18n("DPIO module")},
|
|
{ 0x11, 0x01, i18n("Performance counters")},
|
|
{ 0x11, 0x10, i18n("Communication synchronizer")},
|
|
{ 0x11, 0x20, i18n("Management card")},
|
|
{ 0x11, 0x80, i18n("Signal processing controller")},
|
|
{ 0x11, -1, i18n("Unknown signal processing controller")},
|
|
|
|
{ -1, -1, i18n("Unknown subdevice class")}
|
|
};
|
|
|
|
//keep -1 in last position in "id",
|
|
//in last position in "id2" with certain "id",
|
|
//and in last position in "id3" with certain "id2"
|
|
//device programming interface list
|
|
static const id4name devInterface[]={ { 0x01, 0x05, 0x20, i18n("single DMA")},
|
|
{ 0x01, 0x05, 0x30, i18n("chained DMA")},
|
|
|
|
{ 0x03, 0x00, 0x00, i18n("VGA compatible")},
|
|
{ 0x03, 0x00, 0x01, i18n("8514 compatible")},
|
|
|
|
{ 0x06, 0x04, 0x00, i18n("Normal decode")},
|
|
{ 0x06, 0x04, 0x01, i18n("Subtractive decode")},
|
|
|
|
{ 0x06, 0x08, 0x00, i18n("Transparent mode")},
|
|
{ 0x06, 0x08, 0x01, i18n("Endpoint mode")},
|
|
|
|
{ 0x06, 0x09, 0x40, i18n("Primary bus towards host CPU")},
|
|
{ 0x06, 0x09, 0x40, i18n("Secondary bus towards host CPU")},
|
|
|
|
{ 0x07, 0x00, 0x00, i18n("8250")},
|
|
{ 0x07, 0x00, 0x01, i18n("16450")},
|
|
{ 0x07, 0x00, 0x02, i18n("16550")},
|
|
{ 0x07, 0x00, 0x03, i18n("16650")},
|
|
{ 0x07, 0x00, 0x04, i18n("16750")},
|
|
{ 0x07, 0x00, 0x05, i18n("16850")},
|
|
{ 0x07, 0x00, 0x06, i18n("16950")},
|
|
|
|
{ 0x07, 0x01, 0x00, i18n("SPP")},
|
|
{ 0x07, 0x01, 0x01, i18n("BiDir")},
|
|
{ 0x07, 0x01, 0x02, i18n("ECP")},
|
|
{ 0x07, 0x01, 0x03, i18n("IEEE1284")},
|
|
{ 0x07, 0x01, 0xFE, i18n("IEEE1284 Target")},
|
|
|
|
{ 0x07, 0x03, 0x00, i18n("Generic")},
|
|
{ 0x07, 0x03, 0x01, i18n("Hayes/16450")},
|
|
{ 0x07, 0x03, 0x02, i18n("Hayes/16550")},
|
|
{ 0x07, 0x03, 0x03, i18n("Hayes/16650")},
|
|
{ 0x07, 0x03, 0x04, i18n("Hayes/16750")},
|
|
|
|
{ 0x08, 0x00, 0x00, i18n("8259")},
|
|
{ 0x08, 0x00, 0x01, i18n("ISA PIC")},
|
|
{ 0x08, 0x00, 0x02, i18n("EISA PIC")},
|
|
{ 0x08, 0x00, 0x03, i18n("IO-APIC")},
|
|
{ 0x08, 0x00, 0x04, i18n("IO(X)-APIC")},
|
|
|
|
{ 0x08, 0x01, 0x00, i18n("8237")},
|
|
{ 0x08, 0x01, 0x01, i18n("ISA DMA")},
|
|
{ 0x08, 0x01, 0x01, i18n("EISA DMA")},
|
|
|
|
{ 0x08, 0x02, 0x00, i18n("8254")},
|
|
{ 0x08, 0x02, 0x01, i18n("ISA timer")},
|
|
{ 0x08, 0x02, 0x01, i18n("EISA timers")},
|
|
|
|
{ 0x08, 0x03, 0x00, i18n("Generic")},
|
|
{ 0x08, 0x03, 0x01, i18n("ISA RTC")},
|
|
|
|
{ 0x09, 0x04, 0x00, i18n("Generic")},
|
|
{ 0x09, 0x04, 0x01, i18n("Extended")},
|
|
|
|
{ 0x0C, 0x00, 0x00, i18n("Generic")},
|
|
{ 0x0C, 0x00, 0x01, i18n("OHCI")},
|
|
|
|
{ 0x0C, 0x03, 0x00, i18n("UHCI")},
|
|
{ 0x0C, 0x03, 0x10, i18n("OHCI")},
|
|
{ 0x0C, 0x03, 0x20, i18n("EHCI")},
|
|
{ 0x0C, 0x03, 0x80, i18n("Unspecified")},
|
|
{ 0x0C, 0x03, 0xFE, i18n("USB Device")},
|
|
|
|
{ 0x0C, 0x07, 0x00, i18n("SMIC")},
|
|
{ 0x0C, 0x07, 0x01, i18n("Keyboard controller style")},
|
|
{ 0x0C, 0x07, 0x02, i18n("Block transfer")},
|
|
|
|
{ -1, -1, -1, i18n(strUnknown)}
|
|
};
|
|
|
|
|
|
//keep -1 in last position
|
|
//capabilities list
|
|
static const id2name capNames[]={{ 0x01, i18n("Power management")},
|
|
{ 0x02, i18n("AGP")},
|
|
{ 0x03, i18n("Vital product data")},
|
|
{ 0x04, i18n("Slot identification")},
|
|
{ 0x05, i18n("Message signaled interrupts")},
|
|
{ 0x06, i18n("CompactPCI hot swap")},
|
|
{ 0x07, i18n("PCI-X")},
|
|
{ 0x08, i18n("HyperTransport")},
|
|
{ 0x09, i18n("Vendor specific")},
|
|
{ 0x0A, i18n("Debug port")},
|
|
{ 0x0B, i18n("CompactPCI central resource control")},
|
|
{ 0x0C, i18n("PCI hot-plug")},
|
|
{ 0x0E, i18n("AGP x8")},
|
|
{ 0x0F, i18n("Secure device")},
|
|
{ 0x10, i18n("PCI express")},
|
|
{ 0x11, i18n("MSI-X")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//device selection timing
|
|
static const id2name devSel[]={ { 0x00, i18n("Fast")},
|
|
{ 0x01, i18n("Medium")},
|
|
{ 0x02, i18n("Slow")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//mapping type
|
|
static const id2name mappingType[]={{ 0x00, i18n("32 bit")},
|
|
{ 0x01, i18n("Below 1M")},
|
|
{ 0x02, i18n("64 bit")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//header type
|
|
static const id2name headerType[]={ { 0x00, i18n("Standard")},
|
|
{ 0x01, i18n("Bridge")},
|
|
{ 0x02, i18n("CardBus")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//AGP rate
|
|
static const id2name agpRate[]={{ 0x01, i18n("1X")},
|
|
{ 0x02, i18n("2X")},
|
|
{ 0x03, i18n("1X & 2X")},
|
|
{ 0x04, i18n("4X")},
|
|
{ 0x05, i18n("1X & 4X")},
|
|
{ 0x06, i18n("2X & 4X")},
|
|
{ 0x07, i18n("1X & 2X & 4X")},
|
|
{ 0x09, i18n("4X")},
|
|
{ 0x0A, i18n("8X")},
|
|
{ 0x0B, i18n("4X & 8X")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//AGP calibrating cycle
|
|
static const id2name calCycle[]={ { 0x00, i18n("4 ms")},
|
|
{ 0x01, i18n("16 ms")},
|
|
{ 0x02, i18n("64 ms")},
|
|
{ 0x03, i18n("256 ms")},
|
|
{ 0x07, i18n("Not needed")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//PM auxiliary current
|
|
static const id2name auxCur[]={ { 0x00, i18n("0 (self powered)")},
|
|
{ 0x01, i18n("55 mA")},
|
|
{ 0x02, i18n("100 mA")},
|
|
{ 0x03, i18n("160 mA")},
|
|
{ 0x04, i18n("220 mA")},
|
|
{ 0x05, i18n("270 mA")},
|
|
{ 0x06, i18n("320 mA")},
|
|
{ 0x07, i18n("375 mA")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//PM power state
|
|
static const id2name powerState[]={ { 0x00, i18n("D0")},
|
|
{ 0x01, i18n("D1")},
|
|
{ 0x02, i18n("D2")},
|
|
{ 0x03, i18n("D3 hot")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
//keep -1 in last position
|
|
//MSI multiple message
|
|
static const id2name multipleMessage[]={{ 0x00, i18n("1 vector")},
|
|
{ 0x01, i18n("2 vectors")},
|
|
{ 0x02, i18n("4 vectors")},
|
|
{ 0x03, i18n("8 vectors")},
|
|
{ 0x04, i18n("16 vectors")},
|
|
{ 0x05, i18n("32 vectors")},
|
|
{ -1, i18n(strUnknown)}
|
|
};
|
|
|
|
static const QString& getNameById(const id2name *const table,int id);
|
|
static const QString& getNameBy2Id(const id3name *const table,int id,int id2);
|
|
static const QString& getNameBy3Id(const id4name *const table,int id,int id2, int id3);
|
|
|
|
#endif //KCONTROL_KPCI_PRIVATE_H
|