From d2c6af0269c524567534478dd85debbccbf5367c Mon Sep 17 00:00:00 2001 From: Ivailo Monev Date: Sun, 7 Aug 2016 22:11:45 +0000 Subject: [PATCH] make JavaScriptCore use Katie macros for assertations where possible Signed-off-by: Ivailo Monev --- .../JavaScriptCore/API/APICast.h | 10 +- .../API/JSCallbackObjectFunctions.h | 6 +- .../JavaScriptCore/API/JSClassRef.cpp | 12 +- .../JavaScriptCore/API/JSValueRef.cpp | 2 +- .../JavaScriptCore/assembler/ARMAssembler.cpp | 8 +- .../JavaScriptCore/assembler/ARMAssembler.h | 58 +-- .../JavaScriptCore/assembler/ARMv7Assembler.h | 350 +++++++++--------- .../assembler/AssemblerBuffer.h | 8 +- .../JavaScriptCore/assembler/LinkBuffer.h | 14 +- .../assembler/MacroAssemblerARM.cpp | 2 +- .../assembler/MacroAssemblerARM.h | 24 +- .../assembler/MacroAssemblerARMv7.h | 36 +- .../assembler/MacroAssemblerCodeRef.h | 8 +- .../assembler/MacroAssemblerX86.h | 2 +- .../assembler/MacroAssemblerX86Common.h | 76 ++-- .../assembler/MacroAssemblerX86_64.h | 4 +- .../JavaScriptCore/assembler/X86Assembler.h | 26 +- .../JavaScriptCore/bytecode/CodeBlock.cpp | 32 +- .../JavaScriptCore/bytecode/CodeBlock.h | 34 +- .../JavaScriptCore/bytecode/Instruction.h | 2 +- .../JavaScriptCore/bytecode/SamplingTool.cpp | 6 +- .../JavaScriptCore/bytecode/SamplingTool.h | 16 +- .../bytecompiler/BytecodeGenerator.cpp | 90 ++--- .../bytecompiler/BytecodeGenerator.h | 8 +- .../JavaScriptCore/bytecompiler/Label.h | 2 +- .../JavaScriptCore/bytecompiler/LabelScope.h | 2 +- .../bytecompiler/NodesCodegen.cpp | 36 +- .../JavaScriptCore/bytecompiler/RegisterID.h | 6 +- .../JavaScriptCore/debugger/Debugger.cpp | 6 +- .../JavaScriptCore/generated/Grammar.cpp | 14 +- .../JavaScriptCore/interpreter/CachedCall.h | 4 +- .../JavaScriptCore/interpreter/CallFrame.h | 6 +- .../interpreter/Interpreter.cpp | 98 ++--- .../JavaScriptCore/interpreter/Register.h | 4 +- .../JavaScriptCore/interpreter/RegisterFile.h | 4 +- .../JavaScriptCore/jit/ExecutableAllocator.h | 6 +- .../javascriptcore/JavaScriptCore/jit/JIT.cpp | 24 +- .../JavaScriptCore/jit/JITArithmetic.cpp | 20 +- .../JavaScriptCore/jit/JITCall.cpp | 6 +- .../JavaScriptCore/jit/JITCode.h | 4 +- .../JavaScriptCore/jit/JITInlineMethods.h | 30 +- .../JavaScriptCore/jit/JITOpcodes.cpp | 16 +- .../JavaScriptCore/jit/JITPropertyAccess.cpp | 62 ++-- .../JavaScriptCore/jit/JITStubCall.h | 2 +- .../JavaScriptCore/jit/JITStubs.cpp | 108 +++--- .../JavaScriptCore/parser/Grammar.y | 14 +- .../JavaScriptCore/parser/Lexer.cpp | 28 +- .../JavaScriptCore/parser/NodeConstructors.h | 2 +- .../JavaScriptCore/parser/Nodes.cpp | 14 +- .../JavaScriptCore/parser/Nodes.h | 16 +- .../JavaScriptCore/parser/ParserArena.cpp | 4 +- .../JavaScriptCore/parser/ParserArena.h | 6 +- .../JavaScriptCore/pcre/pcre_compile.cpp | 2 +- .../JavaScriptCore/pcre/pcre_exec.cpp | 18 +- .../JavaScriptCore/pcre/pcre_internal.h | 10 +- .../JavaScriptCore/runtime/ArgList.h | 16 +- .../JavaScriptCore/runtime/Arguments.h | 8 +- .../JavaScriptCore/runtime/ArrayPrototype.cpp | 2 +- .../JavaScriptCore/runtime/BooleanObject.h | 2 +- .../runtime/BooleanPrototype.cpp | 2 +- .../JavaScriptCore/runtime/CallData.cpp | 2 +- .../JavaScriptCore/runtime/Collector.cpp | 48 +-- .../runtime/CollectorHeapIterator.h | 2 +- .../JavaScriptCore/runtime/ConstructData.cpp | 2 +- .../JavaScriptCore/runtime/DateInstance.h | 2 +- .../runtime/ExceptionHelpers.cpp | 2 +- .../JavaScriptCore/runtime/Executable.cpp | 26 +- .../JavaScriptCore/runtime/Executable.h | 10 +- .../runtime/FunctionPrototype.cpp | 4 +- .../JavaScriptCore/runtime/GetterSetter.h | 2 +- .../runtime/GlobalEvalFunction.cpp | 2 +- .../JavaScriptCore/runtime/Identifier.cpp | 4 +- .../JavaScriptCore/runtime/InternalFunction.h | 2 +- .../runtime/JSAPIValueWrapper.h | 2 +- .../JavaScriptCore/runtime/JSActivation.cpp | 14 +- .../JavaScriptCore/runtime/JSActivation.h | 2 +- .../JavaScriptCore/runtime/JSArray.cpp | 44 +-- .../JavaScriptCore/runtime/JSArray.h | 22 +- .../JavaScriptCore/runtime/JSByteArray.cpp | 4 +- .../JavaScriptCore/runtime/JSByteArray.h | 8 +- .../JavaScriptCore/runtime/JSCell.h | 10 +- .../JavaScriptCore/runtime/JSFunction.cpp | 14 +- .../JavaScriptCore/runtime/JSFunction.h | 10 +- .../JavaScriptCore/runtime/JSGlobalObject.cpp | 8 +- .../JavaScriptCore/runtime/JSGlobalObject.h | 10 +- .../JavaScriptCore/runtime/JSImmediate.h | 40 +- .../JavaScriptCore/runtime/JSNumberCell.h | 36 +- .../JavaScriptCore/runtime/JSONObject.cpp | 18 +- .../JavaScriptCore/runtime/JSObject.cpp | 16 +- .../JavaScriptCore/runtime/JSObject.h | 34 +- .../runtime/JSPropertyNameIterator.cpp | 2 +- .../runtime/JSPropertyNameIterator.h | 2 +- .../runtime/JSStaticScopeObject.cpp | 2 +- .../JavaScriptCore/runtime/JSString.cpp | 10 +- .../JavaScriptCore/runtime/JSString.h | 48 +-- .../JavaScriptCore/runtime/JSValue.cpp | 14 +- .../JavaScriptCore/runtime/JSValue.h | 24 +- .../JavaScriptCore/runtime/JSVariableObject.h | 10 +- .../JavaScriptCore/runtime/JSWrapperObject.h | 4 +- .../JavaScriptCore/runtime/LiteralParser.cpp | 8 +- .../JavaScriptCore/runtime/Lookup.cpp | 6 +- .../JavaScriptCore/runtime/Lookup.h | 16 +- .../JavaScriptCore/runtime/MarkStack.cpp | 2 +- .../JavaScriptCore/runtime/MarkStack.h | 14 +- .../runtime/NumberPrototype.cpp | 18 +- .../runtime/ObjectConstructor.cpp | 4 +- .../JavaScriptCore/runtime/Operations.h | 18 +- .../runtime/PropertyDescriptor.cpp | 14 +- .../runtime/PropertyNameArray.cpp | 2 +- .../JavaScriptCore/runtime/PropertySlot.cpp | 2 +- .../JavaScriptCore/runtime/PropertySlot.h | 26 +- .../runtime/PrototypeFunction.cpp | 4 +- .../JavaScriptCore/runtime/PutPropertySlot.h | 2 +- .../JavaScriptCore/runtime/RegExp.cpp | 2 +- .../runtime/RegExpConstructor.cpp | 4 +- .../runtime/RegExpConstructor.h | 4 +- .../JavaScriptCore/runtime/RegExpObject.h | 2 +- .../JavaScriptCore/runtime/ScopeChain.h | 14 +- .../JavaScriptCore/runtime/SmallStrings.cpp | 4 +- .../JavaScriptCore/runtime/StringObject.h | 2 +- .../JavaScriptCore/runtime/Structure.cpp | 122 +++--- .../JavaScriptCore/runtime/Structure.h | 6 +- .../runtime/StructureTransitionTable.h | 22 +- .../JavaScriptCore/runtime/SymbolTable.h | 4 +- .../JavaScriptCore/runtime/TimeoutChecker.h | 2 +- .../JavaScriptCore/runtime/UString.h | 2 +- .../JavaScriptCore/runtime/UStringImpl.cpp | 8 +- .../JavaScriptCore/runtime/UStringImpl.h | 20 +- .../JavaScriptCore/wtf/ASCIICType.h | 8 +- .../JavaScriptCore/wtf/AVLTree.h | 2 +- .../JavaScriptCore/wtf/Assertions.h | 97 +---- .../JavaScriptCore/wtf/ByteArray.cpp | 2 +- .../JavaScriptCore/wtf/ByteArray.h | 2 +- .../wtf/CrossThreadRefCounted.h | 8 +- .../JavaScriptCore/wtf/DateMath.cpp | 10 +- .../JavaScriptCore/wtf/FastMalloc.cpp | 14 +- .../JavaScriptCore/wtf/HashCountedSet.h | 2 +- .../JavaScriptCore/wtf/HashTable.h | 65 ++-- .../JavaScriptCore/wtf/OwnArrayPtr.h | 8 +- .../JavaScriptCore/wtf/OwnPtr.h | 8 +- .../JavaScriptCore/wtf/PassRefPtr.h | 10 +- .../JavaScriptCore/wtf/PtrAndFlags.h | 8 +- .../JavaScriptCore/wtf/RefCounted.h | 8 +- .../JavaScriptCore/wtf/SegmentedVector.h | 8 +- .../JavaScriptCore/wtf/ThreadSpecific.h | 4 +- .../JavaScriptCore/wtf/Vector.h | 28 +- .../JavaScriptCore/wtf/dtoa.cpp | 24 +- .../JavaScriptCore/wtf/qt/ThreadingQt.cpp | 10 +- .../JavaScriptCore/yarr/RegexCompiler.cpp | 32 +- .../JavaScriptCore/yarr/RegexInterpreter.cpp | 104 +++--- .../JavaScriptCore/yarr/RegexJIT.cpp | 42 +-- .../JavaScriptCore/yarr/RegexParser.h | 34 +- .../JavaScriptCore/yarr/RegexPattern.h | 4 +- 153 files changed, 1383 insertions(+), 1467 deletions(-) diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/API/APICast.h b/src/3rdparty/javascriptcore/JavaScriptCore/API/APICast.h index eff7db334..a7d71d571 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/API/APICast.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/API/APICast.h @@ -51,20 +51,20 @@ typedef struct OpaqueJSValue* JSObjectRef; inline JSC::ExecState* toJS(JSContextRef c) { - ASSERT(c); + Q_ASSERT(c); return reinterpret_cast(const_cast(c)); } inline JSC::ExecState* toJS(JSGlobalContextRef c) { - ASSERT(c); + Q_ASSERT(c); return reinterpret_cast(c); } inline JSC::JSValue toJS(JSC::ExecState* exec, JSValueRef v) { ASSERT_UNUSED(exec, exec); - ASSERT(v); + Q_ASSERT(v); #if USE(JSVALUE32_64) JSC::JSCell* jsCell = reinterpret_cast(const_cast(v)); if (!jsCell) @@ -80,7 +80,7 @@ inline JSC::JSValue toJS(JSC::ExecState* exec, JSValueRef v) inline JSC::JSValue toJSForGC(JSC::ExecState* exec, JSValueRef v) { ASSERT_UNUSED(exec, exec); - ASSERT(v); + Q_ASSERT(v); #if USE(JSVALUE32_64) JSC::JSCell* jsCell = reinterpret_cast(const_cast(v)); if (!jsCell) @@ -137,7 +137,7 @@ inline JSContextRef toRef(JSC::ExecState* e) inline JSGlobalContextRef toGlobalRef(JSC::ExecState* e) { - ASSERT(e == e->lexicalGlobalObject()->globalExec()); + Q_ASSERT(e == e->lexicalGlobalObject()->globalExec()); return reinterpret_cast(e); } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/API/JSCallbackObjectFunctions.h b/src/3rdparty/javascriptcore/JavaScriptCore/API/JSCallbackObjectFunctions.h index bb8d0dff6..159003fd3 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/API/JSCallbackObjectFunctions.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/API/JSCallbackObjectFunctions.h @@ -42,7 +42,7 @@ namespace JSC { template inline JSCallbackObject* JSCallbackObject::asCallbackObject(JSValue value) { - ASSERT(asObject(value)->inherits(&info)); + Q_ASSERT(asObject(value)->inherits(&info)); return static_cast(asObject(value)); } @@ -61,14 +61,14 @@ JSCallbackObject::JSCallbackObject(JSClassRef jsClass) : Base() , m_callbackObjectData(new JSCallbackObjectData(0, jsClass)) { - ASSERT(Base::isGlobalObject()); + Q_ASSERT(Base::isGlobalObject()); init(static_cast(this)->globalExec()); } template void JSCallbackObject::init(ExecState* exec) { - ASSERT(exec); + Q_ASSERT(exec); Vector initRoutines; JSClassRef jsClass = classRef(); diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/API/JSClassRef.cpp b/src/3rdparty/javascriptcore/JavaScriptCore/API/JSClassRef.cpp index c6685bfa9..9d6f821a8 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/API/JSClassRef.cpp +++ b/src/3rdparty/javascriptcore/JavaScriptCore/API/JSClassRef.cpp @@ -85,12 +85,12 @@ OpaqueJSClass::OpaqueJSClass(const JSClassDefinition* definition, OpaqueJSClass* OpaqueJSClass::~OpaqueJSClass() { - ASSERT(!m_className.rep()->isIdentifier()); + Q_ASSERT(!m_className.rep()->isIdentifier()); if (m_staticValues) { OpaqueJSClassStaticValuesTable::const_iterator end = m_staticValues->end(); for (OpaqueJSClassStaticValuesTable::const_iterator it = m_staticValues->begin(); it != end; ++it) { - ASSERT(!it->first->isIdentifier()); + Q_ASSERT(!it->first->isIdentifier()); delete it->second; } delete m_staticValues; @@ -99,7 +99,7 @@ OpaqueJSClass::~OpaqueJSClass() if (m_staticFunctions) { OpaqueJSClassStaticFunctionsTable::const_iterator end = m_staticFunctions->end(); for (OpaqueJSClassStaticFunctionsTable::const_iterator it = m_staticFunctions->begin(); it != end; ++it) { - ASSERT(!it->first->isIdentifier()); + Q_ASSERT(!it->first->isIdentifier()); delete it->second; } delete m_staticFunctions; @@ -117,7 +117,7 @@ PassRefPtr OpaqueJSClass::createNoAutomaticPrototype(const JSClas static void clearReferenceToPrototype(JSObjectRef prototype) { OpaqueJSClassContextData* jsClassData = static_cast(JSObjectGetPrivate(prototype)); - ASSERT(jsClassData); + Q_ASSERT(jsClassData); jsClassData->cachedPrototype = 0; } @@ -142,7 +142,7 @@ OpaqueJSClassContextData::OpaqueJSClassContextData(OpaqueJSClass* jsClass) staticValues = new OpaqueJSClassStaticValuesTable; OpaqueJSClassStaticValuesTable::const_iterator end = jsClass->m_staticValues->end(); for (OpaqueJSClassStaticValuesTable::const_iterator it = jsClass->m_staticValues->begin(); it != end; ++it) { - ASSERT(!it->first->isIdentifier()); + Q_ASSERT(!it->first->isIdentifier()); // Use a local variable here to sidestep an RVCT compiler bug. StaticValueEntry* entry = new StaticValueEntry(it->second->getProperty, it->second->setProperty, it->second->attributes); staticValues->add(UString::Rep::create(it->first->data(), it->first->size()), entry); @@ -157,7 +157,7 @@ OpaqueJSClassContextData::OpaqueJSClassContextData(OpaqueJSClass* jsClass) staticFunctions = new OpaqueJSClassStaticFunctionsTable; OpaqueJSClassStaticFunctionsTable::const_iterator end = jsClass->m_staticFunctions->end(); for (OpaqueJSClassStaticFunctionsTable::const_iterator it = jsClass->m_staticFunctions->begin(); it != end; ++it) { - ASSERT(!it->first->isIdentifier()); + Q_ASSERT(!it->first->isIdentifier()); // Use a local variable here to sidestep an RVCT compiler bug. StaticFunctionEntry* entry = new StaticFunctionEntry(it->second->callAsFunction, it->second->attributes); staticFunctions->add(UString::Rep::create(it->first->data(), it->first->size()), entry); diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/API/JSValueRef.cpp b/src/3rdparty/javascriptcore/JavaScriptCore/API/JSValueRef.cpp index a12cc3409..028d77eb8 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/API/JSValueRef.cpp +++ b/src/3rdparty/javascriptcore/JavaScriptCore/API/JSValueRef.cpp @@ -61,7 +61,7 @@ using namespace JSC; return kJSTypeNumber; if (jsValue.isString()) return kJSTypeString; - ASSERT(jsValue.isObject()); + Q_ASSERT(jsValue.isObject()); return kJSTypeObject; } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.cpp b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.cpp index 6dd2b87ff..8fafb06ba 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.cpp +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.cpp @@ -40,10 +40,10 @@ void ARMAssembler::patchConstantPoolLoad(void* loadAddr, void* constPoolAddr) ARMWord diff = reinterpret_cast(constPoolAddr) - ldr; ARMWord index = (*ldr & 0xfff) >> 1; - ASSERT(diff >= 1); + Q_ASSERT(diff >= 1); if (diff >= 2 || index > 0) { diff = (diff + index - 2) * sizeof(ARMWord); - ASSERT(diff <= 0xfff); + Q_ASSERT(diff <= 0xfff); *ldr = (*ldr & ~0xfff) | diff; } else *ldr = (*ldr & ~(0xfff | ARMAssembler::DT_UP)) | sizeof(ARMWord); @@ -126,7 +126,7 @@ int ARMAssembler::genInt(int reg, ARMWord imm, bool positive) } } - ASSERT((imm & 0xff) == 0); + Q_ASSERT((imm & 0xff) == 0); if ((imm & 0xff000000) == 0) { imm1 = OP2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8); @@ -292,7 +292,7 @@ void ARMAssembler::baseIndexTransfer32(bool isLoad, RegisterID srcDst, RegisterI { ARMWord op2; - ASSERT(scale >= 0 && scale <= 3); + Q_ASSERT(scale >= 0 && scale <= 3); op2 = lsl(index, scale); if (offset >= 0 && offset <= 0xfff) { diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.h index 6967b37a8..5d2abbb60 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMAssembler.h @@ -218,7 +218,7 @@ namespace JSC { : m_offset(offset) , m_used(false) { - ASSERT(m_offset == offset); + Q_ASSERT(m_offset == offset); } int m_offset : 31; @@ -346,13 +346,13 @@ namespace JSC { #if WTF_ARM_ARCH_AT_LEAST(7) void movw_r(int rd, ARMWord op2, Condition cc = AL) { - ASSERT((op2 | 0xf0fff) == 0xf0fff); + Q_ASSERT((op2 | 0xf0fff) == 0xf0fff); m_buffer.putInt(static_cast(cc) | MOVW | RD(rd) | op2); } void movt_r(int rd, ARMWord op2, Condition cc = AL) { - ASSERT((op2 | 0xf0fff) == 0xf0fff); + Q_ASSERT((op2 | 0xf0fff) == 0xf0fff); m_buffer.putInt(static_cast(cc) | MOVT | RD(rd) | op2); } #endif @@ -474,25 +474,25 @@ namespace JSC { void fdtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL) { - ASSERT(op2 <= 0xff); + Q_ASSERT(op2 <= 0xff); emitInst(static_cast(cc) | FDTR | DT_UP | (isLoad ? DT_LOAD : 0), rd, rb, op2); } void fdtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL) { - ASSERT(op2 <= 0xff); + Q_ASSERT(op2 <= 0xff); emitInst(static_cast(cc) | FDTR | (isLoad ? DT_LOAD : 0), rd, rb, op2); } void push_r(int reg, Condition cc = AL) { - ASSERT(ARMWord(reg) <= 0xf); + Q_ASSERT(ARMWord(reg) <= 0xf); m_buffer.putInt(cc | DTR | DT_WB | RN(ARMRegisters::sp) | RD(reg) | 0x4); } void pop_r(int reg, Condition cc = AL) { - ASSERT(ARMWord(reg) <= 0xf); + Q_ASSERT(ARMWord(reg) <= 0xf); m_buffer.putInt(cc | (DTR ^ DT_PRE) | DT_LOAD | DT_UP | RN(ARMRegisters::sp) | RD(reg) | 0x4); } @@ -550,43 +550,43 @@ namespace JSC { static ARMWord lsl(int reg, ARMWord value) { - ASSERT(reg <= ARMRegisters::pc); - ASSERT(value <= 0x1f); + Q_ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(value <= 0x1f); return reg | (value << 7) | 0x00; } static ARMWord lsr(int reg, ARMWord value) { - ASSERT(reg <= ARMRegisters::pc); - ASSERT(value <= 0x1f); + Q_ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(value <= 0x1f); return reg | (value << 7) | 0x20; } static ARMWord asr(int reg, ARMWord value) { - ASSERT(reg <= ARMRegisters::pc); - ASSERT(value <= 0x1f); + Q_ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(value <= 0x1f); return reg | (value << 7) | 0x40; } static ARMWord lsl_r(int reg, int shiftReg) { - ASSERT(reg <= ARMRegisters::pc); - ASSERT(shiftReg <= ARMRegisters::pc); + Q_ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(shiftReg <= ARMRegisters::pc); return reg | (shiftReg << 8) | 0x10; } static ARMWord lsr_r(int reg, int shiftReg) { - ASSERT(reg <= ARMRegisters::pc); - ASSERT(shiftReg <= ARMRegisters::pc); + Q_ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(shiftReg <= ARMRegisters::pc); return reg | (shiftReg << 8) | 0x30; } static ARMWord asr_r(int reg, int shiftReg) { - ASSERT(reg <= ARMRegisters::pc); - ASSERT(shiftReg <= ARMRegisters::pc); + Q_ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(shiftReg <= ARMRegisters::pc); return reg | (shiftReg << 8) | 0x50; } @@ -636,7 +636,7 @@ namespace JSC { static ARMWord* getLdrImmAddress(ARMWord* insn) { // Must be an ldr ..., [pc +/- imm] - ASSERT((*insn & 0x0f7f0000) == 0x051f0000); + Q_ASSERT((*insn & 0x0f7f0000) == 0x051f0000); ARMWord addr = reinterpret_cast(insn) + DefaultPrefetching * sizeof(ARMWord); if (*insn & DT_UP) @@ -647,7 +647,7 @@ namespace JSC { static ARMWord* getLdrImmAddressOnPool(ARMWord* insn, uint32_t* constPool) { // Must be an ldr ..., [pc +/- imm] - ASSERT((*insn & 0x0f7f0000) == 0x051f0000); + Q_ASSERT((*insn & 0x0f7f0000) == 0x051f0000); if (*insn & 0x1) return reinterpret_cast(constPool + ((*insn & SDT_OFFSET_MASK) >> 1)); @@ -664,7 +664,7 @@ namespace JSC { static ARMWord patchConstantPoolLoad(ARMWord load, ARMWord value) { value = (value << 1) + 1; - ASSERT(!(value & ~0xfff)); + Q_ASSERT(!(value & ~0xfff)); return (load & ~0xfff) | value; } @@ -692,7 +692,7 @@ namespace JSC { // On arm, this is a patch from LDR to ADD. It is restricted conversion, // from special case to special case, altough enough for its purpose ARMWord* insn = reinterpret_cast(from); - ASSERT((*insn & 0x0ff00f00) == 0x05900000); + Q_ASSERT((*insn & 0x0ff00f00) == 0x05900000); *insn = (*insn & 0xf00ff0ff) | 0x02800000; ExecutableAllocator::cacheFlush(insn, sizeof(ARMWord)); @@ -760,7 +760,7 @@ namespace JSC { static ARMWord getOp2Byte(ARMWord imm) { - ASSERT(imm <= 0xff); + Q_ASSERT(imm <= 0xff); return OP2_IMMh | (imm & 0x0f) | ((imm & 0xf0) << 4) ; } @@ -789,32 +789,32 @@ namespace JSC { static ARMWord placeConstantPoolBarrier(int offset) { offset = (offset - sizeof(ARMWord)) >> 2; - ASSERT((offset <= BOFFSET_MAX && offset >= BOFFSET_MIN)); + Q_ASSERT((offset <= BOFFSET_MAX && offset >= BOFFSET_MIN)); return AL | B | (offset & BRANCH_MASK); } private: ARMWord RM(int reg) { - ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(reg <= ARMRegisters::pc); return reg; } ARMWord RS(int reg) { - ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(reg <= ARMRegisters::pc); return reg << 8; } ARMWord RD(int reg) { - ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(reg <= ARMRegisters::pc); return reg << 12; } ARMWord RN(int reg) { - ASSERT(reg <= ARMRegisters::pc); + Q_ASSERT(reg <= ARMRegisters::pc); return reg << 16; } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h index 4e394b206..05397b68f 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h @@ -259,7 +259,7 @@ public: int32_t leadingZeros = countLeadingZeros(value); // if there were 24 or more leading zeros, then we'd have hit the (value < 256) case. - ASSERT(leadingZeros < 24); + Q_ASSERT(leadingZeros < 24); // Given a number with bit fields Z:B:C, where count(Z)+count(B)+count(C) == 32, // Z are the bits known zero, B is the 8-bit immediate, C are the bits to check for @@ -337,16 +337,16 @@ public: bool isUInt10() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xfc00); } bool isUInt12() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xf000); } bool isUInt16() { return m_type == TypeUInt16; } - uint8_t getUInt3() { ASSERT(isUInt3()); return m_value.asInt; } - uint8_t getUInt4() { ASSERT(isUInt4()); return m_value.asInt; } - uint8_t getUInt5() { ASSERT(isUInt5()); return m_value.asInt; } - uint8_t getUInt6() { ASSERT(isUInt6()); return m_value.asInt; } - uint8_t getUInt7() { ASSERT(isUInt7()); return m_value.asInt; } - uint8_t getUInt8() { ASSERT(isUInt8()); return m_value.asInt; } - uint8_t getUInt9() { ASSERT(isUInt9()); return m_value.asInt; } - uint8_t getUInt10() { ASSERT(isUInt10()); return m_value.asInt; } - uint16_t getUInt12() { ASSERT(isUInt12()); return m_value.asInt; } - uint16_t getUInt16() { ASSERT(isUInt16()); return m_value.asInt; } + uint8_t getUInt3() { Q_ASSERT(isUInt3()); return m_value.asInt; } + uint8_t getUInt4() { Q_ASSERT(isUInt4()); return m_value.asInt; } + uint8_t getUInt5() { Q_ASSERT(isUInt5()); return m_value.asInt; } + uint8_t getUInt6() { Q_ASSERT(isUInt6()); return m_value.asInt; } + uint8_t getUInt7() { Q_ASSERT(isUInt7()); return m_value.asInt; } + uint8_t getUInt8() { Q_ASSERT(isUInt8()); return m_value.asInt; } + uint8_t getUInt9() { Q_ASSERT(isUInt9()); return m_value.asInt; } + uint8_t getUInt10() { Q_ASSERT(isUInt10()); return m_value.asInt; } + uint16_t getUInt12() { Q_ASSERT(isUInt12()); return m_value.asInt; } + uint16_t getUInt16() { Q_ASSERT(isUInt16()); return m_value.asInt; } bool isEncodedImm() { return m_type == TypeEncoded; } @@ -414,7 +414,7 @@ class ARMv7Assembler { public: ~ARMv7Assembler() { - ASSERT(m_jumpsToLink.isEmpty()); + Q_ASSERT(m_jumpsToLink.isEmpty()); } typedef ARMRegisters::RegisterID RegisterID; @@ -478,7 +478,7 @@ public: : m_offset(offset) , m_used(false) { - ASSERT(m_offset == offset); + Q_ASSERT(m_offset == offset); } int m_offset : 31; @@ -523,19 +523,19 @@ private: uint32_t singleRegisterNum(FPRegisterID reg) { - ASSERT(isSingleRegister(reg)); + Q_ASSERT(isSingleRegister(reg)); return reg; } uint32_t doubleRegisterNum(FPRegisterID reg) { - ASSERT(isDoubleRegister(reg)); + Q_ASSERT(isDoubleRegister(reg)); return reg >> 1; } uint32_t quadRegisterNum(FPRegisterID reg) { - ASSERT(isQuadRegister(reg)); + Q_ASSERT(isQuadRegister(reg)); return reg >> 2; } @@ -685,7 +685,7 @@ private: | (ifThenElseConditionBit(condition, inst3if) << 2) | (ifThenElseConditionBit(condition, inst4if) << 1) | 1; - ASSERT((condition != ConditionAL) || (mask & (mask - 1))); + Q_ASSERT((condition != ConditionAL) || (mask & (mask - 1))); return (condition << 4) | mask; } uint8_t ifThenElse(Condition condition, bool inst2if, bool inst3if) @@ -693,21 +693,21 @@ private: int mask = (ifThenElseConditionBit(condition, inst2if) << 3) | (ifThenElseConditionBit(condition, inst3if) << 2) | 2; - ASSERT((condition != ConditionAL) || (mask & (mask - 1))); + Q_ASSERT((condition != ConditionAL) || (mask & (mask - 1))); return (condition << 4) | mask; } uint8_t ifThenElse(Condition condition, bool inst2if) { int mask = (ifThenElseConditionBit(condition, inst2if) << 3) | 4; - ASSERT((condition != ConditionAL) || (mask & (mask - 1))); + Q_ASSERT((condition != ConditionAL) || (mask & (mask - 1))); return (condition << 4) | mask; } uint8_t ifThenElse(Condition condition) { int mask = 8; - ASSERT((condition != ConditionAL) || (mask & (mask - 1))); + Q_ASSERT((condition != ConditionAL) || (mask & (mask - 1))); return (condition << 4) | mask; } @@ -716,10 +716,10 @@ public: void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) { // Rd can only be SP if Rn is also SP. - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(imm.isValid()); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(imm.isValid()); if (rn == ARMRegisters::sp) { if (!(rd & 8) && imm.isUInt10()) { @@ -742,17 +742,17 @@ public: if (imm.isEncodedImm()) m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_imm_T3, rn, rd, imm); else { - ASSERT(imm.isUInt12()); + Q_ASSERT(imm.isUInt12()); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_imm_T4, rn, rd, imm); } } void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(!BadReg(rm)); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_ADD_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -773,10 +773,10 @@ public: void add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) { // Rd can only be SP if Rn is also SP. - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(imm.isEncodedImm()); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(imm.isEncodedImm()); if (!((rd | rn) & 8)) { if (imm.isUInt3()) { @@ -794,10 +794,10 @@ public: // Not allowed in an IT (if then) block? void add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(!BadReg(rm)); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_ADD_S_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -812,17 +812,17 @@ public: void ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(imm.isEncodedImm()); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(imm.isEncodedImm()); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_AND_imm_T1, rn, rd, imm); } void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_AND_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -838,17 +838,17 @@ public: void asr(RegisterID rd, RegisterID rm, int32_t shiftAmount) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rm)); ShiftTypeAndAmount shift(SRType_ASR, shiftAmount); m_formatter.twoWordOp16FourFours(OP_ASR_imm_T1, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } void asr(RegisterID rd, RegisterID rn, RegisterID rm) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_ASR_reg_T2, rn, FourFours(0xf, rd, 0, rm)); } @@ -862,7 +862,7 @@ public: // Only allowed in IT (if then) block if last instruction. JmpSrc blx(RegisterID rm) { - ASSERT(rm != ARMRegisters::pc); + Q_ASSERT(rm != ARMRegisters::pc); m_formatter.oneWordOp8RegReg143(OP_BLX, rm, (RegisterID)8); return JmpSrc(m_formatter.size()); } @@ -881,16 +881,16 @@ public: void cmn(RegisterID rn, ARMThumbImmediate imm) { - ASSERT(rn != ARMRegisters::pc); - ASSERT(imm.isEncodedImm()); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(imm.isEncodedImm()); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_CMN_imm, rn, (RegisterID)0xf, imm); } void cmp(RegisterID rn, ARMThumbImmediate imm) { - ASSERT(rn != ARMRegisters::pc); - ASSERT(imm.isEncodedImm()); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(imm.isEncodedImm()); if (!(rn & 8) && imm.isUInt8()) m_formatter.oneWordOp5Reg3Imm8(OP_CMP_imm_T1, rn, imm.getUInt8()); @@ -900,8 +900,8 @@ public: void cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT(rn != ARMRegisters::pc); - ASSERT(!BadReg(rm)); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_CMP_reg_T2, rn, FourFours(shift.hi4(), 0xf, shift.lo4(), rm)); } @@ -916,18 +916,18 @@ public: // xor is not spelled with an 'e'. :-( void eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(imm.isEncodedImm()); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(imm.isEncodedImm()); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_EOR_imm_T1, rn, rd, imm); } // xor is not spelled with an 'e'. :-( void eor(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_EOR_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -965,8 +965,8 @@ public: // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. void ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) { - ASSERT(rn != ARMRegisters::pc); // LDR (literal) - ASSERT(imm.isUInt12()); + Q_ASSERT(rn != ARMRegisters::pc); // LDR (literal) + Q_ASSERT(imm.isUInt12()); if (!((rt | rn) & 8) && imm.isUInt7()) m_formatter.oneWordOp5Imm5Reg3Reg3(OP_LDR_imm_T1, imm.getUInt7() >> 2, rn, rt); @@ -989,17 +989,17 @@ public: // if (wback) REG[rn] = _tmp void ldr(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) { - ASSERT(rt != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(index || wback); - ASSERT(!wback | (rt != rn)); + Q_ASSERT(rt != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(index || wback); + Q_ASSERT(!wback | (rt != rn)); bool add = true; if (offset < 0) { add = false; offset = -offset; } - ASSERT((offset & ~0xff) == 0); + Q_ASSERT((offset & ~0xff) == 0); offset |= (wback << 8); offset |= (add << 9); @@ -1012,9 +1012,9 @@ public: // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. void ldr(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0) { - ASSERT(rn != ARMRegisters::pc); // LDR (literal) - ASSERT(!BadReg(rm)); - ASSERT(shift <= 3); + Q_ASSERT(rn != ARMRegisters::pc); // LDR (literal) + Q_ASSERT(!BadReg(rm)); + Q_ASSERT(shift <= 3); if (!shift && !((rt | rn | rm) & 8)) m_formatter.oneWordOp7Reg3Reg3Reg3(OP_LDR_reg_T1, rm, rn, rt); @@ -1025,8 +1025,8 @@ public: // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. void ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) { - ASSERT(rn != ARMRegisters::pc); // LDR (literal) - ASSERT(imm.isUInt12()); + Q_ASSERT(rn != ARMRegisters::pc); // LDR (literal) + Q_ASSERT(imm.isUInt12()); if (!((rt | rn) & 8) && imm.isUInt6()) m_formatter.oneWordOp5Imm5Reg3Reg3(OP_LDRH_imm_T1, imm.getUInt6() >> 2, rn, rt); @@ -1047,17 +1047,17 @@ public: // if (wback) REG[rn] = _tmp void ldrh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) { - ASSERT(rt != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(index || wback); - ASSERT(!wback | (rt != rn)); + Q_ASSERT(rt != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(index || wback); + Q_ASSERT(!wback | (rt != rn)); bool add = true; if (offset < 0) { add = false; offset = -offset; } - ASSERT((offset & ~0xff) == 0); + Q_ASSERT((offset & ~0xff) == 0); offset |= (wback << 8); offset |= (add << 9); @@ -1069,10 +1069,10 @@ public: void ldrh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0) { - ASSERT(!BadReg(rt)); // Memory hint - ASSERT(rn != ARMRegisters::pc); // LDRH (literal) - ASSERT(!BadReg(rm)); - ASSERT(shift <= 3); + Q_ASSERT(!BadReg(rt)); // Memory hint + Q_ASSERT(rn != ARMRegisters::pc); // LDRH (literal) + Q_ASSERT(!BadReg(rm)); + Q_ASSERT(shift <= 3); if (!shift && !((rt | rn | rm) & 8)) m_formatter.oneWordOp7Reg3Reg3Reg3(OP_LDRH_reg_T1, rm, rn, rt); @@ -1082,49 +1082,49 @@ public: void lsl(RegisterID rd, RegisterID rm, int32_t shiftAmount) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rm)); ShiftTypeAndAmount shift(SRType_LSL, shiftAmount); m_formatter.twoWordOp16FourFours(OP_LSL_imm_T1, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } void lsl(RegisterID rd, RegisterID rn, RegisterID rm) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_LSL_reg_T2, rn, FourFours(0xf, rd, 0, rm)); } void lsr(RegisterID rd, RegisterID rm, int32_t shiftAmount) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rm)); ShiftTypeAndAmount shift(SRType_LSR, shiftAmount); m_formatter.twoWordOp16FourFours(OP_LSR_imm_T1, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } void lsr(RegisterID rd, RegisterID rn, RegisterID rm) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_LSR_reg_T2, rn, FourFours(0xf, rd, 0, rm)); } void movT3(RegisterID rd, ARMThumbImmediate imm) { - ASSERT(imm.isValid()); - ASSERT(!imm.isEncodedImm()); - ASSERT(!BadReg(rd)); + Q_ASSERT(imm.isValid()); + Q_ASSERT(!imm.isEncodedImm()); + Q_ASSERT(!BadReg(rd)); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_MOV_imm_T3, imm.m_value.imm4, rd, imm); } void mov(RegisterID rd, ARMThumbImmediate imm) { - ASSERT(imm.isValid()); - ASSERT(!BadReg(rd)); + Q_ASSERT(imm.isValid()); + Q_ASSERT(!BadReg(rd)); if ((rd < 8) && imm.isUInt8()) m_formatter.oneWordOp5Reg3Imm8(OP_MOV_imm_T1, rd, imm.getUInt8()); @@ -1141,23 +1141,23 @@ public: void movt(RegisterID rd, ARMThumbImmediate imm) { - ASSERT(imm.isUInt16()); - ASSERT(!BadReg(rd)); + Q_ASSERT(imm.isUInt16()); + Q_ASSERT(!BadReg(rd)); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_MOVT, imm.m_value.imm4, rd, imm); } void mvn(RegisterID rd, ARMThumbImmediate imm) { - ASSERT(imm.isEncodedImm()); - ASSERT(!BadReg(rd)); + Q_ASSERT(imm.isEncodedImm()); + Q_ASSERT(!BadReg(rd)); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_MVN_imm, 0xf, rd, imm); } void mvn(RegisterID rd, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp16FourFours(OP_MVN_reg_T2, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -1171,17 +1171,17 @@ public: void orr(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(imm.isEncodedImm()); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(imm.isEncodedImm()); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ORR_imm_T1, rn, rd, imm); } void orr(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_ORR_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -1197,36 +1197,36 @@ public: void ror(RegisterID rd, RegisterID rm, int32_t shiftAmount) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rm)); ShiftTypeAndAmount shift(SRType_ROR, shiftAmount); m_formatter.twoWordOp16FourFours(OP_ROR_imm_T1, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } void ror(RegisterID rd, RegisterID rn, RegisterID rm) { - ASSERT(!BadReg(rd)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rd)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_ROR_reg_T2, rn, FourFours(0xf, rd, 0, rm)); } void smull(RegisterID rdLo, RegisterID rdHi, RegisterID rn, RegisterID rm) { - ASSERT(!BadReg(rdLo)); - ASSERT(!BadReg(rdHi)); - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); - ASSERT(rdLo != rdHi); + Q_ASSERT(!BadReg(rdLo)); + Q_ASSERT(!BadReg(rdHi)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); + Q_ASSERT(rdLo != rdHi); m_formatter.twoWordOp12Reg4FourFours(OP_SMULL_T1, rn, FourFours(rdLo, rdHi, 0, rm)); } // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. void str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) { - ASSERT(rt != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(imm.isUInt12()); + Q_ASSERT(rt != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(imm.isUInt12()); if (!((rt | rn) & 8) && imm.isUInt7()) m_formatter.oneWordOp5Imm5Reg3Reg3(OP_STR_imm_T1, imm.getUInt7() >> 2, rn, rt); @@ -1249,17 +1249,17 @@ public: // if (wback) REG[rn] = _tmp void str(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) { - ASSERT(rt != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(index || wback); - ASSERT(!wback | (rt != rn)); + Q_ASSERT(rt != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(index || wback); + Q_ASSERT(!wback | (rt != rn)); bool add = true; if (offset < 0) { add = false; offset = -offset; } - ASSERT((offset & ~0xff) == 0); + Q_ASSERT((offset & ~0xff) == 0); offset |= (wback << 8); offset |= (add << 9); @@ -1272,9 +1272,9 @@ public: // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. void str(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0) { - ASSERT(rn != ARMRegisters::pc); - ASSERT(!BadReg(rm)); - ASSERT(shift <= 3); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(!BadReg(rm)); + Q_ASSERT(shift <= 3); if (!shift && !((rt | rn | rm) & 8)) m_formatter.oneWordOp7Reg3Reg3Reg3(OP_STR_reg_T1, rm, rn, rt); @@ -1285,10 +1285,10 @@ public: void sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) { // Rd can only be SP if Rn is also SP. - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(imm.isValid()); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(imm.isValid()); if ((rn == ARMRegisters::sp) && (rd == ARMRegisters::sp) && imm.isUInt9()) { m_formatter.oneWordOp9Imm7(OP_SUB_SP_imm_T1, imm.getUInt9() >> 2); @@ -1306,17 +1306,17 @@ public: if (imm.isEncodedImm()) m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_SUB_imm_T3, rn, rd, imm); else { - ASSERT(imm.isUInt12()); + Q_ASSERT(imm.isUInt12()); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_SUB_imm_T4, rn, rd, imm); } } void sub(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(!BadReg(rm)); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_SUB_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -1333,10 +1333,10 @@ public: void sub_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) { // Rd can only be SP if Rn is also SP. - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(imm.isValid()); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(imm.isValid()); if ((rn == ARMRegisters::sp) && (rd == ARMRegisters::sp) && imm.isUInt9()) { m_formatter.oneWordOp9Imm7(OP_SUB_SP_imm_T1, imm.getUInt9() >> 2); @@ -1357,10 +1357,10 @@ public: // Not allowed in an IT (if then) block? void sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); - ASSERT(rd != ARMRegisters::pc); - ASSERT(rn != ARMRegisters::pc); - ASSERT(!BadReg(rm)); + Q_ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); + Q_ASSERT(rd != ARMRegisters::pc); + Q_ASSERT(rn != ARMRegisters::pc); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_SUB_S_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm)); } @@ -1375,16 +1375,16 @@ public: void tst(RegisterID rn, ARMThumbImmediate imm) { - ASSERT(!BadReg(rn)); - ASSERT(imm.isEncodedImm()); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(imm.isEncodedImm()); m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_TST_imm, rn, (RegisterID)0xf, imm); } void tst(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) { - ASSERT(!BadReg(rn)); - ASSERT(!BadReg(rm)); + Q_ASSERT(!BadReg(rn)); + Q_ASSERT(!BadReg(rm)); m_formatter.twoWordOp12Reg4FourFours(OP_TST_reg_T2, rn, FourFours(shift.hi4(), 0xf, shift.lo4(), rm)); } @@ -1468,14 +1468,14 @@ public: static void* getRelocatedAddress(void* code, JmpSrc jump) { - ASSERT(jump.m_offset != -1); + Q_ASSERT(jump.m_offset != -1); return reinterpret_cast(reinterpret_cast(code) + jump.m_offset); } static void* getRelocatedAddress(void* code, JmpDst destination) { - ASSERT(destination.m_offset != -1); + Q_ASSERT(destination.m_offset != -1); return reinterpret_cast(reinterpret_cast(code) + destination.m_offset); } @@ -1514,13 +1514,13 @@ public: } m_jumpsToLink.clear(); - ASSERT(copy); + Q_ASSERT(copy); return copy; } static unsigned getCallReturnOffset(JmpSrc call) { - ASSERT(call.m_offset >= 0); + Q_ASSERT(call.m_offset >= 0); return call.m_offset; } @@ -1534,14 +1534,14 @@ public: void linkJump(JmpSrc from, JmpDst to) { - ASSERT(to.m_offset != -1); - ASSERT(from.m_offset != -1); + Q_ASSERT(to.m_offset != -1); + Q_ASSERT(from.m_offset != -1); m_jumpsToLink.append(LinkRecord(from.m_offset, to.m_offset)); } static void linkJump(void* code, JmpSrc from, void* to) { - ASSERT(from.m_offset != -1); + Q_ASSERT(from.m_offset != -1); uint16_t* location = reinterpret_cast(reinterpret_cast(code) + from.m_offset); linkJumpAbsolute(location, to); @@ -1551,9 +1551,9 @@ public: // return a bool saying whether the link was successful? static void linkCall(void* code, JmpSrc from, void* to) { - ASSERT(!(reinterpret_cast(code) & 1)); - ASSERT(from.m_offset != -1); - ASSERT(reinterpret_cast(to) & 1); + Q_ASSERT(!(reinterpret_cast(code) & 1)); + Q_ASSERT(from.m_offset != -1); + Q_ASSERT(reinterpret_cast(to) & 1); setPointer(reinterpret_cast(reinterpret_cast(code) + from.m_offset) - 1, to); } @@ -1565,8 +1565,8 @@ public: static void relinkJump(void* from, void* to) { - ASSERT(!(reinterpret_cast(from) & 1)); - ASSERT(!(reinterpret_cast(to) & 1)); + Q_ASSERT(!(reinterpret_cast(from) & 1)); + Q_ASSERT(!(reinterpret_cast(to) & 1)); linkJumpAbsolute(reinterpret_cast(from), to); @@ -1575,8 +1575,8 @@ public: static void relinkCall(void* from, void* to) { - ASSERT(!(reinterpret_cast(from) & 1)); - ASSERT(reinterpret_cast(to) & 1); + Q_ASSERT(!(reinterpret_cast(from) & 1)); + Q_ASSERT(reinterpret_cast(to) & 1); setPointer(reinterpret_cast(from) - 1, to); @@ -1585,7 +1585,7 @@ public: static void repatchInt32(void* where, int32_t value) { - ASSERT(!(reinterpret_cast(where) & 1)); + Q_ASSERT(!(reinterpret_cast(where) & 1)); setInt32(where, value); @@ -1594,7 +1594,7 @@ public: static void repatchPointer(void* where, void* value) { - ASSERT(!(reinterpret_cast(where) & 1)); + Q_ASSERT(!(reinterpret_cast(where) & 1)); setPointer(where, value); @@ -1603,10 +1603,10 @@ public: static void repatchLoadPtrToLEA(void* where) { - ASSERT(!(reinterpret_cast(where) & 1)); + Q_ASSERT(!(reinterpret_cast(where) & 1)); uint16_t* loadOp = reinterpret_cast(where) + 4; - ASSERT((*loadOp & 0xfff0) == OP_LDR_reg_T2); + Q_ASSERT((*loadOp & 0xfff0) == OP_LDR_reg_T2); *loadOp = OP_ADD_reg_T3 | (*loadOp & 0xf); ExecutableAllocator::cacheFlush(loadOp, sizeof(uint16_t)); @@ -1630,7 +1630,7 @@ private: // offset is effectively leftshifted by 2 already (the bottom two bits are zero, and not // reperesented in the instruction. Left shift by 14, to mov it into position 0x00AA0000. - ASSERT((offset & ~(0xff << 2)) == 0); + Q_ASSERT((offset & ~(0xff << 2)) == 0); offset <<= 14; m_formatter.vfpOp(0x0b00ed00 | offset | (up << 7) | (isLoad << 4) | doubleRegisterMask(rd, 6, 28) | rn); @@ -1639,7 +1639,7 @@ private: static void setInt32(void* code, uint32_t value) { uint16_t* location = reinterpret_cast(code); - ASSERT(isMOV_imm_T3(location - 4) && isMOVT(location - 2)); + Q_ASSERT(isMOV_imm_T3(location - 4) && isMOVT(location - 2)); ARMThumbImmediate lo16 = ARMThumbImmediate::makeUInt16(static_cast(value)); ARMThumbImmediate hi16 = ARMThumbImmediate::makeUInt16(static_cast(value >> 16)); @@ -1697,10 +1697,10 @@ private: // FIMXE: this should be up in the MacroAssembler layer. :-( const uint16_t JUMP_TEMPORARY_REGISTER = ARMRegisters::ip; - ASSERT(!(reinterpret_cast(instruction) & 1)); - ASSERT(!(reinterpret_cast(target) & 1)); + Q_ASSERT(!(reinterpret_cast(instruction) & 1)); + Q_ASSERT(!(reinterpret_cast(target) & 1)); - ASSERT( (isMOV_imm_T3(instruction - 5) && isMOVT(instruction - 3) && isBX(instruction - 1)) + Q_ASSERT( (isMOV_imm_T3(instruction - 5) && isMOVT(instruction - 3) && isBX(instruction - 1)) || (isNOP_T1(instruction - 5) && isNOP_T2(instruction - 4) && isB(instruction - 2)) ); intptr_t relative = reinterpret_cast(target) - (reinterpret_cast(instruction)); @@ -1710,7 +1710,7 @@ private: relative ^= 0xC00000; // All branch offsets should be an even distance. - ASSERT(!(relative & 1)); + Q_ASSERT(!(relative & 1)); // There may be a better way to fix this, but right now put the NOPs first, since in the // case of an conditional branch this will be coming after an ITTT predicating *three* // instructions! Looking backwards to modify the ITTT to an IT is not easy, due to diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/AssemblerBuffer.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/AssemblerBuffer.h index 104d75828..9be61da08 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/AssemblerBuffer.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/AssemblerBuffer.h @@ -67,7 +67,7 @@ namespace JSC { void putByteUnchecked(int value) { - ASSERT(!(m_size > m_capacity - 4)); + Q_ASSERT(!(m_size > m_capacity - 4)); m_buffer[m_size] = value; m_size++; } @@ -81,7 +81,7 @@ namespace JSC { void putShortUnchecked(int value) { - ASSERT(!(m_size > m_capacity - 4)); + Q_ASSERT(!(m_size > m_capacity - 4)); *reinterpret_cast(&m_buffer[m_size]) = value; m_size += 2; } @@ -95,14 +95,14 @@ namespace JSC { void putIntUnchecked(int value) { - ASSERT(!(m_size > m_capacity - 4)); + Q_ASSERT(!(m_size > m_capacity - 4)); *reinterpret_cast(&m_buffer[m_size]) = value; m_size += 4; } void putInt64Unchecked(int64_t value) { - ASSERT(!(m_size > m_capacity - 8)); + Q_ASSERT(!(m_size > m_capacity - 8)); *reinterpret_cast(&m_buffer[m_size]) = value; m_size += 8; } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/LinkBuffer.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/LinkBuffer.h index dbe873aff..f42eb1e7e 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/LinkBuffer.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/LinkBuffer.h @@ -74,14 +74,14 @@ public: ~LinkBuffer() { - ASSERT(m_completed); + Q_ASSERT(m_completed); } // These methods are used to link or set values at code generation time. void link(Call call, FunctionPtr function) { - ASSERT(call.isFlagSet(Call::Linkable)); + Q_ASSERT(call.isFlagSet(Call::Linkable)); MacroAssembler::linkCall(m_code, call, function); } @@ -110,15 +110,15 @@ public: CodeLocationCall locationOf(Call call) { - ASSERT(call.isFlagSet(Call::Linkable)); - ASSERT(!call.isFlagSet(Call::Near)); + Q_ASSERT(call.isFlagSet(Call::Linkable)); + Q_ASSERT(!call.isFlagSet(Call::Near)); return CodeLocationCall(MacroAssembler::getLinkerAddress(m_code, call.m_jmp)); } CodeLocationNearCall locationOfNearCall(Call call) { - ASSERT(call.isFlagSet(Call::Linkable)); - ASSERT(call.isFlagSet(Call::Near)); + Q_ASSERT(call.isFlagSet(Call::Linkable)); + Q_ASSERT(call.isFlagSet(Call::Near)); return CodeLocationNearCall(MacroAssembler::getLinkerAddress(m_code, call.m_jmp)); } @@ -158,7 +158,7 @@ private: void performFinalization() { #ifndef NDEBUG - ASSERT(!m_completed); + Q_ASSERT(!m_completed); m_completed = true; #endif diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.cpp b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.cpp index 17e053f9c..03031e383 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.cpp +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.cpp @@ -47,7 +47,7 @@ void MacroAssemblerARM::load32WithUnalignedHalfWords(BaseIndex address, Register { ARMWord op2; - ASSERT(address.scale >= 0 && address.scale <= 3); + Q_ASSERT(address.scale >= 0 && address.scale <= 3); op2 = m_assembler.lsl(address.index, static_cast(address.scale)); if (address.offset >= 0 && address.offset + 0x2 <= 0xff) { diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.h index 3c493c551..d00966673 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARM.h @@ -121,7 +121,7 @@ public: void lshift32(RegisterID shift_amount, RegisterID dest) { ARMWord w = ARMAssembler::getOp2(0x1f); - ASSERT(w != ARMAssembler::INVALID_IMM); + Q_ASSERT(w != ARMAssembler::INVALID_IMM); m_assembler.and_r(ARMRegisters::S0, shift_amount, w); m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0)); @@ -170,7 +170,7 @@ public: void rshift32(RegisterID shift_amount, RegisterID dest) { ARMWord w = ARMAssembler::getOp2(0x1f); - ASSERT(w != ARMAssembler::INVALID_IMM); + Q_ASSERT(w != ARMAssembler::INVALID_IMM); m_assembler.and_r(ARMRegisters::S0, shift_amount, w); m_assembler.movs_r(dest, m_assembler.asr_r(dest, ARMRegisters::S0)); @@ -424,14 +424,14 @@ public: Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); m_assembler.tst_r(reg, mask); return Jump(m_assembler.jmp(ARMCondition(cond))); } Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1)) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true); if (w & ARMAssembler::OP2_INV_IMM) m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::OP2_INV_IMM); @@ -469,14 +469,14 @@ public: Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); add32(src, dest); return Jump(m_assembler.jmp(ARMCondition(cond))); } Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); add32(imm, dest); return Jump(m_assembler.jmp(ARMCondition(cond))); } @@ -493,7 +493,7 @@ public: Jump branchMul32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); if (cond == Overflow) { mull32(src, dest, dest); cond = NonZero; @@ -505,7 +505,7 @@ public: Jump branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); if (cond == Overflow) { move(imm, ARMRegisters::S0); mull32(ARMRegisters::S0, src, dest); @@ -518,28 +518,28 @@ public: Jump branchSub32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); sub32(src, dest); return Jump(m_assembler.jmp(ARMCondition(cond))); } Jump branchSub32(Condition cond, Imm32 imm, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); sub32(imm, dest); return Jump(m_assembler.jmp(ARMCondition(cond))); } Jump branchNeg32(Condition cond, RegisterID srcDest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); neg32(srcDest); return Jump(m_assembler.jmp(ARMCondition(cond))); } Jump branchOr32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero)); or32(src, dest); return Jump(m_assembler.jmp(ARMCondition(cond))); } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARMv7.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARMv7.h index 32bed946d..3c53f93b5 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARMv7.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerARMv7.h @@ -201,7 +201,7 @@ public: { // Clamp the shift to the range 0..31 ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f); - ASSERT(armImm.isValid()); + Q_ASSERT(armImm.isValid()); m_assembler.ARM_and(dataTempRegister, shift_amount, armImm); m_assembler.lsl(dest, dest, dataTempRegister); @@ -248,7 +248,7 @@ public: { // Clamp the shift to the range 0..31 ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f); - ASSERT(armImm.isValid()); + Q_ASSERT(armImm.isValid()); m_assembler.ARM_and(dataTempRegister, shift_amount, armImm); m_assembler.asr(dest, dest, dataTempRegister); @@ -346,10 +346,10 @@ private: m_assembler.ldr(dest, address.base, address.u.index, address.u.scale); else if (address.u.offset >= 0) { ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset); - ASSERT(armImm.isValid()); + Q_ASSERT(armImm.isValid()); m_assembler.ldr(dest, address.base, armImm); } else { - ASSERT(address.u.offset >= -255); + Q_ASSERT(address.u.offset >= -255); m_assembler.ldr(dest, address.base, address.u.offset, true, false); } } @@ -360,10 +360,10 @@ private: m_assembler.ldrh(dest, address.base, address.u.index, address.u.scale); else if (address.u.offset >= 0) { ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset); - ASSERT(armImm.isValid()); + Q_ASSERT(armImm.isValid()); m_assembler.ldrh(dest, address.base, armImm); } else { - ASSERT(address.u.offset >= -255); + Q_ASSERT(address.u.offset >= -255); m_assembler.ldrh(dest, address.base, address.u.offset, true, false); } } @@ -374,10 +374,10 @@ private: m_assembler.str(src, address.base, address.u.index, address.u.scale); else if (address.u.offset >= 0) { ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset); - ASSERT(armImm.isValid()); + Q_ASSERT(armImm.isValid()); m_assembler.str(src, address.base, armImm); } else { - ASSERT(address.u.offset >= -255); + Q_ASSERT(address.u.offset >= -255); m_assembler.str(src, address.base, address.u.offset, true, false); } } @@ -795,21 +795,21 @@ public: Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); m_assembler.tst(reg, mask); return Jump(makeBranch(cond)); } Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1)) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); test32(reg, mask); return Jump(makeBranch(cond)); } Jump branchTest32(Condition cond, Address address, Imm32 mask = Imm32(-1)) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); // use addressTempRegister incase the branchTest32 we call uses dataTempRegister. :-/ load32(address, addressTempRegister); return branchTest32(cond, addressTempRegister, mask); @@ -817,7 +817,7 @@ public: Jump branchTest32(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1)) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); // use addressTempRegister incase the branchTest32 we call uses dataTempRegister. :-/ load32(address, addressTempRegister); return branchTest32(cond, addressTempRegister, mask); @@ -853,14 +853,14 @@ public: Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); m_assembler.add_S(dest, dest, src); return Jump(makeBranch(cond)); } Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value); if (armImm.isValid()) m_assembler.add_S(dest, dest, armImm); @@ -873,7 +873,7 @@ public: Jump branchMul32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT(cond == Overflow); + Q_ASSERT(cond == Overflow); m_assembler.smull(dest, dataTempRegister, dest, src); m_assembler.asr(addressTempRegister, dest, 31); return branch32(NotEqual, addressTempRegister, dataTempRegister); @@ -881,7 +881,7 @@ public: Jump branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest) { - ASSERT(cond == Overflow); + Q_ASSERT(cond == Overflow); move(imm, dataTempRegister); m_assembler.smull(dest, dataTempRegister, src, dataTempRegister); m_assembler.asr(addressTempRegister, dest, 31); @@ -890,14 +890,14 @@ public: Jump branchSub32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); m_assembler.sub_S(dest, dest, src); return Jump(makeBranch(cond)); } Jump branchSub32(Condition cond, Imm32 imm, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value); if (armImm.isValid()) m_assembler.sub_S(dest, dest, armImm); diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerCodeRef.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerCodeRef.h index cae8bf68e..8d47bab7d 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerCodeRef.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerCodeRef.h @@ -44,13 +44,13 @@ // decorated and undectorated null, and the second test ensures that the pointer is // decorated. #define ASSERT_VALID_CODE_POINTER(ptr) \ - ASSERT(reinterpret_cast(ptr) & ~1); \ - ASSERT(reinterpret_cast(ptr) & 1) + Q_ASSERT(reinterpret_cast(ptr) & ~1); \ + Q_ASSERT(reinterpret_cast(ptr) & 1) #define ASSERT_VALID_CODE_OFFSET(offset) \ - ASSERT(!(offset & 1)) // Must be multiple of 2. + Q_ASSERT(!(offset & 1)) // Must be multiple of 2. #else #define ASSERT_VALID_CODE_POINTER(ptr) \ - ASSERT(ptr) + Q_ASSERT(ptr) #define ASSERT_VALID_CODE_OFFSET(offset) // Anything goes! #endif diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86.h index ca7c31a07..0dbcb6717 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86.h @@ -91,7 +91,7 @@ public: void loadDouble(void* address, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.movsd_mr(address, dest); } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86Common.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86Common.h index cc8ba3734..cdaabf522 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86Common.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86Common.h @@ -365,79 +365,79 @@ public: void loadDouble(ImplicitAddress address, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.movsd_mr(address.offset, address.base, dest); } void storeDouble(FPRegisterID src, ImplicitAddress address) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.movsd_rm(src, address.offset, address.base); } void addDouble(FPRegisterID src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.addsd_rr(src, dest); } void addDouble(Address src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.addsd_mr(src.offset, src.base, dest); } void divDouble(FPRegisterID src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.divsd_rr(src, dest); } void divDouble(Address src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.divsd_mr(src.offset, src.base, dest); } void subDouble(FPRegisterID src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.subsd_rr(src, dest); } void subDouble(Address src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.subsd_mr(src.offset, src.base, dest); } void mulDouble(FPRegisterID src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.mulsd_rr(src, dest); } void mulDouble(Address src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.mulsd_mr(src.offset, src.base, dest); } void convertInt32ToDouble(RegisterID src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.cvtsi2sd_rr(src, dest); } void convertInt32ToDouble(Address src, FPRegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.cvtsi2sd_mr(src.offset, src.base, dest); } Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); if (cond & DoubleConditionBitInvert) m_assembler.ucomisd_rr(left, right); @@ -458,7 +458,7 @@ public: return result; } - ASSERT(!(cond & DoubleConditionBitSpecial)); + Q_ASSERT(!(cond & DoubleConditionBitSpecial)); return Jump(m_assembler.jCC(static_cast(cond & ~DoubleConditionBits))); } @@ -468,7 +468,7 @@ public: // (specifically, in this case, INT_MIN). Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.cvttsd2si_rr(src, dest); return branch32(Equal, dest, Imm32(0x80000000)); } @@ -479,7 +479,7 @@ public: // (specifically, in this case, 0). void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.cvttsd2si_rr(src, dest); // If the result is zero, it might have been -0.0, and the double comparison won't catch this! @@ -494,7 +494,7 @@ public: void zeroDouble(FPRegisterID srcDest) { - ASSERT(isSSE2Present()); + Q_ASSERT(isSSE2Present()); m_assembler.xorpd_rr(srcDest, srcDest); } @@ -672,7 +672,7 @@ public: Jump branch16(Condition cond, BaseIndex left, Imm32 right) { - ASSERT(!(right.m_value & 0xFFFF0000)); + Q_ASSERT(!(right.m_value & 0xFFFF0000)); m_assembler.cmpw_im(right.m_value, left.offset, left.base, left.index, left.scale); return Jump(m_assembler.jCC(x86Condition(cond))); @@ -680,14 +680,14 @@ public: Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); m_assembler.testl_rr(reg, mask); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1)) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); // if we are only interested in the low seven bits, this can be tested with a testb if (mask.m_value == -1) m_assembler.testl_rr(reg, reg); @@ -700,7 +700,7 @@ public: Jump branchTest32(Condition cond, Address address, Imm32 mask = Imm32(-1)) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); if (mask.m_value == -1) m_assembler.cmpl_im(0, address.offset, address.base); else @@ -710,7 +710,7 @@ public: Jump branchTest32(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1)) { - ASSERT((cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Zero) || (cond == NonZero)); if (mask.m_value == -1) m_assembler.cmpl_im(0, address.offset, address.base, address.index, address.scale); else @@ -747,105 +747,105 @@ public: Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); add32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); add32(imm, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchAdd32(Condition cond, Imm32 src, Address dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); add32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchAdd32(Condition cond, RegisterID src, Address dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); add32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchAdd32(Condition cond, Address src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); add32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchMul32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT(cond == Overflow); + Q_ASSERT(cond == Overflow); mul32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchMul32(Condition cond, Address src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); mul32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest) { - ASSERT(cond == Overflow); + Q_ASSERT(cond == Overflow); mul32(imm, src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchSub32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); sub32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchSub32(Condition cond, Imm32 imm, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); sub32(imm, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchSub32(Condition cond, Imm32 imm, Address dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); sub32(imm, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchSub32(Condition cond, RegisterID src, Address dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); sub32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchSub32(Condition cond, Address src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); sub32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchNeg32(Condition cond, RegisterID srcDest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); neg32(srcDest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchOr32(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero)); or32(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } @@ -996,7 +996,7 @@ private: s_sse2CheckState = (flags & SSE2FeatureBit) ? HasSSE2 : NoSSE2; } // Only check once. - ASSERT(s_sse2CheckState != NotCheckedSSE2); + Q_ASSERT(s_sse2CheckState != NotCheckedSSE2); return s_sse2CheckState == HasSSE2; } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86_64.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86_64.h index 07c9fa7cb..2b5147c92 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86_64.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/MacroAssemblerX86_64.h @@ -374,14 +374,14 @@ public: Jump branchAddPtr(Condition cond, RegisterID src, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); addPtr(src, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } Jump branchSubPtr(Condition cond, Imm32 imm, RegisterID dest) { - ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); + Q_ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero)); subPtr(imm, dest); return Jump(m_assembler.jCC(x86Condition(cond))); } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/X86Assembler.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/X86Assembler.h index c185dd598..9a52ae7a7 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/X86Assembler.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/X86Assembler.h @@ -253,7 +253,7 @@ public: : m_offset(offset) , m_used(false) { - ASSERT(m_offset == offset); + Q_ASSERT(m_offset == offset); } int m_offset : 31; @@ -1485,8 +1485,8 @@ public: void linkJump(JmpSrc from, JmpDst to) { - ASSERT(from.m_offset != -1); - ASSERT(to.m_offset != -1); + Q_ASSERT(from.m_offset != -1); + Q_ASSERT(to.m_offset != -1); char* code = reinterpret_cast(m_formatter.data()); setRel32(code + from.m_offset, code + to.m_offset); @@ -1494,21 +1494,21 @@ public: static void linkJump(void* code, JmpSrc from, void* to) { - ASSERT(from.m_offset != -1); + Q_ASSERT(from.m_offset != -1); setRel32(reinterpret_cast(code) + from.m_offset, to); } static void linkCall(void* code, JmpSrc from, void* to) { - ASSERT(from.m_offset != -1); + Q_ASSERT(from.m_offset != -1); setRel32(reinterpret_cast(code) + from.m_offset, to); } static void linkPointer(void* code, JmpDst where, void* value) { - ASSERT(where.m_offset != -1); + Q_ASSERT(where.m_offset != -1); setPointer(reinterpret_cast(code) + where.m_offset, value); } @@ -1545,20 +1545,20 @@ public: static unsigned getCallReturnOffset(JmpSrc call) { - ASSERT(call.m_offset >= 0); + Q_ASSERT(call.m_offset >= 0); return call.m_offset; } static void* getRelocatedAddress(void* code, JmpSrc jump) { - ASSERT(jump.m_offset != -1); + Q_ASSERT(jump.m_offset != -1); return reinterpret_cast(reinterpret_cast(code) + jump.m_offset); } static void* getRelocatedAddress(void* code, JmpDst destination) { - ASSERT(destination.m_offset != -1); + Q_ASSERT(destination.m_offset != -1); return reinterpret_cast(reinterpret_cast(code) + destination.m_offset); } @@ -1581,7 +1581,7 @@ public: void* executableCopy(ExecutablePool* allocator) { void* copy = m_formatter.executableCopy(allocator); - ASSERT(copy); + Q_ASSERT(copy); return copy; } @@ -1600,7 +1600,7 @@ private: static void setRel32(void* from, void* to) { intptr_t offset = reinterpret_cast(to) - reinterpret_cast(from); - ASSERT(offset == static_cast(offset)); + Q_ASSERT(offset == static_cast(offset)); setInt32(from, offset); } @@ -1953,7 +1953,7 @@ private: void putModRmSib(ModRmMode mode, int reg, RegisterID base, RegisterID index, int scale) { - ASSERT(mode != ModRmRegister); + Q_ASSERT(mode != ModRmRegister); putModRm(mode, reg, hasSib); m_buffer.putByteUnchecked((scale << 6) | ((index & 7) << 3) | (base & 7)); @@ -2016,7 +2016,7 @@ private: void memoryModRM(int reg, RegisterID base, RegisterID index, int scale, int offset) { - ASSERT(index != noIndex); + Q_ASSERT(index != noIndex); #if CPU(X86_64) if (!offset && (base != noBase) && (base != noBase2)) diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.cpp b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.cpp index cb7be1901..8977ceaee 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.cpp +++ b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.cpp @@ -317,7 +317,7 @@ void CodeBlock::printStructures(const Instruction* vPC) const } // These m_instructions doesn't ref Structures. - ASSERT(vPC[0].u.opcode == op_get_by_id_generic || vPC[0].u.opcode == op_put_by_id_generic || vPC[0].u.opcode == op_call || vPC[0].u.opcode == op_call_eval || vPC[0].u.opcode == op_construct); + Q_ASSERT(vPC[0].u.opcode == op_get_by_id_generic || vPC[0].u.opcode == op_put_by_id_generic || vPC[0].u.opcode == op_call || vPC[0].u.opcode == op_call_eval || vPC[0].u.opcode == op_construct); } void CodeBlock::dump(ExecState* exec) const @@ -445,7 +445,7 @@ void CodeBlock::dump(ExecState* exec) const for (Vector::const_iterator iter = m_rareData->m_characterSwitchJumpTables[i].branchOffsets.begin(); iter != end; ++iter, ++entry) { if (!*iter) continue; - ASSERT(!((i + m_rareData->m_characterSwitchJumpTables[i].min) & ~0xFFFF)); + Q_ASSERT(!((i + m_rareData->m_characterSwitchJumpTables[i].min) & ~0xFFFF)); UChar ch = static_cast(entry + m_rareData->m_characterSwitchJumpTables[i].min); printf("\t\t\"%s\" => %04d\n", UString(&ch, 1).ascii(), *iter); } @@ -1277,7 +1277,7 @@ CodeBlock::CodeBlock(ScriptExecutable* ownerExecutable, CodeType codeType, PassR , m_symbolTable(symTab) , m_exceptionInfo(new ExceptionInfo) { - ASSERT(m_source); + Q_ASSERT(m_source); #if DUMP_CODE_BLOCK_STATISTICS liveCodeBlockSet.add(this); @@ -1311,7 +1311,7 @@ CodeBlock::~CodeBlock() if (Structure* structure = m_methodCallLinkInfos[i].cachedStructure) { structure->deref(); // Both members must be filled at the same time - ASSERT(!!m_methodCallLinkInfos[i].cachedPrototypeStructure); + Q_ASSERT(!!m_methodCallLinkInfos[i].cachedPrototypeStructure); m_methodCallLinkInfos[i].cachedPrototypeStructure->deref(); } } @@ -1380,7 +1380,7 @@ void CodeBlock::derefStructures(Instruction* vPC) const } // These instructions don't ref their Structures. - ASSERT(vPC[0].u.opcode == op_get_by_id || vPC[0].u.opcode == op_put_by_id || vPC[0].u.opcode == op_get_by_id_generic || vPC[0].u.opcode == op_put_by_id_generic || vPC[0].u.opcode == op_get_array_length || vPC[0].u.opcode == op_get_string_length); + Q_ASSERT(vPC[0].u.opcode == op_get_by_id || vPC[0].u.opcode == op_put_by_id || vPC[0].u.opcode == op_get_by_id_generic || vPC[0].u.opcode == op_put_by_id_generic || vPC[0].u.opcode == op_get_array_length || vPC[0].u.opcode == op_get_string_length); } void CodeBlock::refStructures(Instruction* vPC) const @@ -1411,7 +1411,7 @@ void CodeBlock::refStructures(Instruction* vPC) const } // These instructions don't ref their Structures. - ASSERT(vPC[0].u.opcode == op_get_by_id || vPC[0].u.opcode == op_put_by_id || vPC[0].u.opcode == op_get_by_id_generic || vPC[0].u.opcode == op_put_by_id_generic); + Q_ASSERT(vPC[0].u.opcode == op_get_by_id || vPC[0].u.opcode == op_put_by_id || vPC[0].u.opcode == op_get_by_id_generic || vPC[0].u.opcode == op_put_by_id_generic); } void CodeBlock::markAggregate(MarkStack& markStack) @@ -1437,7 +1437,7 @@ void CodeBlock::reparseForExceptionInfoIfNecessary(CallFrame* callFrame) scopeDelta -= static_cast(this)->baseScopeDepth(); else if (m_codeType == FunctionCode) scopeDelta++; // Compilation of function code assumes activation is not on the scope chain yet. - ASSERT(scopeDelta >= 0); + Q_ASSERT(scopeDelta >= 0); while (scopeDelta--) scopeChain = scopeChain->next; } @@ -1447,7 +1447,7 @@ void CodeBlock::reparseForExceptionInfoIfNecessary(CallFrame* callFrame) HandlerInfo* CodeBlock::handlerForBytecodeOffset(unsigned bytecodeOffset) { - ASSERT(bytecodeOffset < m_instructionCount); + Q_ASSERT(bytecodeOffset < m_instructionCount); if (!m_rareData) return 0; @@ -1465,10 +1465,10 @@ HandlerInfo* CodeBlock::handlerForBytecodeOffset(unsigned bytecodeOffset) int CodeBlock::lineNumberForBytecodeOffset(CallFrame* callFrame, unsigned bytecodeOffset) { - ASSERT(bytecodeOffset < m_instructionCount); + Q_ASSERT(bytecodeOffset < m_instructionCount); reparseForExceptionInfoIfNecessary(callFrame); - ASSERT(m_exceptionInfo); + Q_ASSERT(m_exceptionInfo); if (!m_exceptionInfo->m_lineInfo.size()) return m_ownerExecutable->source().firstLine(); // Empty function @@ -1490,10 +1490,10 @@ int CodeBlock::lineNumberForBytecodeOffset(CallFrame* callFrame, unsigned byteco int CodeBlock::expressionRangeForBytecodeOffset(CallFrame* callFrame, unsigned bytecodeOffset, int& divot, int& startOffset, int& endOffset) { - ASSERT(bytecodeOffset < m_instructionCount); + Q_ASSERT(bytecodeOffset < m_instructionCount); reparseForExceptionInfoIfNecessary(callFrame); - ASSERT(m_exceptionInfo); + Q_ASSERT(m_exceptionInfo); if (!m_exceptionInfo->m_expressionInfo.size()) { // We didn't think anything could throw. Apparently we were wrong. @@ -1513,7 +1513,7 @@ int CodeBlock::expressionRangeForBytecodeOffset(CallFrame* callFrame, unsigned b high = mid; } - ASSERT(low); + Q_ASSERT(low); if (!low) { startOffset = 0; endOffset = 0; @@ -1529,10 +1529,10 @@ int CodeBlock::expressionRangeForBytecodeOffset(CallFrame* callFrame, unsigned b bool CodeBlock::getByIdExceptionInfoForBytecodeOffset(CallFrame* callFrame, unsigned bytecodeOffset, OpcodeID& opcodeID) { - ASSERT(bytecodeOffset < m_instructionCount); + Q_ASSERT(bytecodeOffset < m_instructionCount); reparseForExceptionInfoIfNecessary(callFrame); - ASSERT(m_exceptionInfo); + Q_ASSERT(m_exceptionInfo); if (!m_exceptionInfo->m_getByIdExceptionInfo.size()) return false; @@ -1557,7 +1557,7 @@ bool CodeBlock::getByIdExceptionInfoForBytecodeOffset(CallFrame* callFrame, unsi #if ENABLE(JIT) bool CodeBlock::functionRegisterForBytecodeOffset(unsigned bytecodeOffset, int& functionRegisterIndex) { - ASSERT(bytecodeOffset < m_instructionCount); + Q_ASSERT(bytecodeOffset < m_instructionCount); if (!m_rareData || !m_rareData->m_functionRegisterInfos.size()) return false; diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.h b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.h index ad8b847fa..d9cdf514b 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/CodeBlock.h @@ -238,12 +238,12 @@ namespace JSC { } // 'size' should never reach zero. - ASSERT(size); + Q_ASSERT(size); } // If we reach this point we've chopped down to one element, no need to check it matches - ASSERT(size == 1); - ASSERT(key == valueAtPosition(&array[0])); + Q_ASSERT(size == 1); + Q_ASSERT(key == valueAtPosition(&array[0])); return &array[0]; } #endif @@ -412,21 +412,21 @@ namespace JSC { size_t numberOfExceptionHandlers() const { return m_rareData ? m_rareData->m_exceptionHandlers.size() : 0; } void addExceptionHandler(const HandlerInfo& hanler) { createRareDataIfNecessary(); return m_rareData->m_exceptionHandlers.append(hanler); } - HandlerInfo& exceptionHandler(int index) { ASSERT(m_rareData); return m_rareData->m_exceptionHandlers[index]; } + HandlerInfo& exceptionHandler(int index) { Q_ASSERT(m_rareData); return m_rareData->m_exceptionHandlers[index]; } bool hasExceptionInfo() const { return m_exceptionInfo; } void clearExceptionInfo() { m_exceptionInfo.clear(); } - ExceptionInfo* extractExceptionInfo() { ASSERT(m_exceptionInfo); return m_exceptionInfo.release(); } + ExceptionInfo* extractExceptionInfo() { Q_ASSERT(m_exceptionInfo); return m_exceptionInfo.release(); } - void addExpressionInfo(const ExpressionRangeInfo& expressionInfo) { ASSERT(m_exceptionInfo); m_exceptionInfo->m_expressionInfo.append(expressionInfo); } - void addGetByIdExceptionInfo(const GetByIdExceptionInfo& info) { ASSERT(m_exceptionInfo); m_exceptionInfo->m_getByIdExceptionInfo.append(info); } + void addExpressionInfo(const ExpressionRangeInfo& expressionInfo) { Q_ASSERT(m_exceptionInfo); m_exceptionInfo->m_expressionInfo.append(expressionInfo); } + void addGetByIdExceptionInfo(const GetByIdExceptionInfo& info) { Q_ASSERT(m_exceptionInfo); m_exceptionInfo->m_getByIdExceptionInfo.append(info); } - size_t numberOfLineInfos() const { ASSERT(m_exceptionInfo); return m_exceptionInfo->m_lineInfo.size(); } - void addLineInfo(const LineInfo& lineInfo) { ASSERT(m_exceptionInfo); m_exceptionInfo->m_lineInfo.append(lineInfo); } - LineInfo& lastLineInfo() { ASSERT(m_exceptionInfo); return m_exceptionInfo->m_lineInfo.last(); } + size_t numberOfLineInfos() const { Q_ASSERT(m_exceptionInfo); return m_exceptionInfo->m_lineInfo.size(); } + void addLineInfo(const LineInfo& lineInfo) { Q_ASSERT(m_exceptionInfo); m_exceptionInfo->m_lineInfo.append(lineInfo); } + LineInfo& lastLineInfo() { Q_ASSERT(m_exceptionInfo); return m_exceptionInfo->m_lineInfo.last(); } #if ENABLE(JIT) - Vector& callReturnIndexVector() { ASSERT(m_exceptionInfo); return m_exceptionInfo->m_callReturnIndexVector; } + Vector& callReturnIndexVector() { Q_ASSERT(m_exceptionInfo); return m_exceptionInfo->m_callReturnIndexVector; } #endif // Constant Pool @@ -448,26 +448,26 @@ namespace JSC { FunctionExecutable* functionExpr(int index) { return m_functionExprs[index].get(); } unsigned addRegExp(RegExp* r) { createRareDataIfNecessary(); unsigned size = m_rareData->m_regexps.size(); m_rareData->m_regexps.append(r); return size; } - RegExp* regexp(int index) const { ASSERT(m_rareData); return m_rareData->m_regexps[index].get(); } + RegExp* regexp(int index) const { Q_ASSERT(m_rareData); return m_rareData->m_regexps[index].get(); } // Jump Tables size_t numberOfImmediateSwitchJumpTables() const { return m_rareData ? m_rareData->m_immediateSwitchJumpTables.size() : 0; } SimpleJumpTable& addImmediateSwitchJumpTable() { createRareDataIfNecessary(); m_rareData->m_immediateSwitchJumpTables.append(SimpleJumpTable()); return m_rareData->m_immediateSwitchJumpTables.last(); } - SimpleJumpTable& immediateSwitchJumpTable(int tableIndex) { ASSERT(m_rareData); return m_rareData->m_immediateSwitchJumpTables[tableIndex]; } + SimpleJumpTable& immediateSwitchJumpTable(int tableIndex) { Q_ASSERT(m_rareData); return m_rareData->m_immediateSwitchJumpTables[tableIndex]; } size_t numberOfCharacterSwitchJumpTables() const { return m_rareData ? m_rareData->m_characterSwitchJumpTables.size() : 0; } SimpleJumpTable& addCharacterSwitchJumpTable() { createRareDataIfNecessary(); m_rareData->m_characterSwitchJumpTables.append(SimpleJumpTable()); return m_rareData->m_characterSwitchJumpTables.last(); } - SimpleJumpTable& characterSwitchJumpTable(int tableIndex) { ASSERT(m_rareData); return m_rareData->m_characterSwitchJumpTables[tableIndex]; } + SimpleJumpTable& characterSwitchJumpTable(int tableIndex) { Q_ASSERT(m_rareData); return m_rareData->m_characterSwitchJumpTables[tableIndex]; } size_t numberOfStringSwitchJumpTables() const { return m_rareData ? m_rareData->m_stringSwitchJumpTables.size() : 0; } StringJumpTable& addStringSwitchJumpTable() { createRareDataIfNecessary(); m_rareData->m_stringSwitchJumpTables.append(StringJumpTable()); return m_rareData->m_stringSwitchJumpTables.last(); } - StringJumpTable& stringSwitchJumpTable(int tableIndex) { ASSERT(m_rareData); return m_rareData->m_stringSwitchJumpTables[tableIndex]; } + StringJumpTable& stringSwitchJumpTable(int tableIndex) { Q_ASSERT(m_rareData); return m_rareData->m_stringSwitchJumpTables[tableIndex]; } SymbolTable* symbolTable() { return m_symbolTable; } - SharedSymbolTable* sharedSymbolTable() { ASSERT(m_codeType == FunctionCode); return static_cast(m_symbolTable); } + SharedSymbolTable* sharedSymbolTable() { Q_ASSERT(m_codeType == FunctionCode); return static_cast(m_symbolTable); } EvalCodeCache& evalCodeCache() { createRareDataIfNecessary(); return m_rareData->m_evalCodeCache; } @@ -609,7 +609,7 @@ namespace JSC { unsigned numVariables() { return m_variables.size(); } void adoptVariables(Vector& variables) { - ASSERT(m_variables.isEmpty()); + Q_ASSERT(m_variables.isEmpty()); m_variables.swap(variables); } diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/Instruction.h b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/Instruction.h index dc7615b9d..62febc315 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/Instruction.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/Instruction.h @@ -109,7 +109,7 @@ namespace JSC { for (int i = 0; i < count; ++i) { PolymorphicStubInfo& info = list[i]; - ASSERT(info.base); + Q_ASSERT(info.base); info.base->deref(); if (info.u.proto) { diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.cpp b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.cpp index 7ad585187..1fc92b8bb 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.cpp +++ b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.cpp @@ -124,7 +124,7 @@ void* SamplingThread::threadStartFunc(void*) void SamplingThread::start(unsigned hertz) { - ASSERT(!s_running); + Q_ASSERT(!s_running); s_running = true; s_hertz = hertz; @@ -133,7 +133,7 @@ void SamplingThread::start(unsigned hertz) void SamplingThread::stop() { - ASSERT(s_running); + Q_ASSERT(s_running); s_running = false; waitForThreadCompletion(s_samplingThread, 0); } @@ -180,7 +180,7 @@ void SamplingTool::doRun() if (CodeBlock* codeBlock = sample.codeBlock()) { QMutexLocker locker(m_scriptSampleMapMutex); ScriptSampleRecord* record = m_scopeSampleMap->get(codeBlock->ownerExecutable()); - ASSERT(record); + Q_ASSERT(record); record->sample(codeBlock, sample.vPC()); } #endif diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.h b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.h index c3e62472a..1c8ce950e 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.h +++ b/src/3rdparty/javascriptcore/JavaScriptCore/bytecode/SamplingTool.h @@ -49,15 +49,15 @@ namespace JSC { #if ENABLE(SAMPLING_FLAGS) static void setFlag(unsigned flag) { - ASSERT(flag >= 1); - ASSERT(flag <= 32); + Q_ASSERT(flag >= 1); + Q_ASSERT(flag <= 32); s_flags |= 1u << (flag - 1); } static void clearFlag(unsigned flag) { - ASSERT(flag >= 1); - ASSERT(flag <= 32); + Q_ASSERT(flag >= 1); + Q_ASSERT(flag <= 32); s_flags &= ~(1u << (flag - 1)); } @@ -220,7 +220,7 @@ namespace JSC { void sample(CodeBlock* codeBlock, Instruction* vPC) { - ASSERT(!(reinterpret_cast(vPC) & 0x3)); + Q_ASSERT(!(reinterpret_cast(vPC) & 0x3)); m_codeBlock = codeBlock; m_sample = reinterpret_cast(vPC); } @@ -230,7 +230,7 @@ namespace JSC { void* encodeSample(Instruction* vPC, bool inCTIFunction = false, bool inHostFunction = false) { - ASSERT(!(reinterpret_cast(vPC) & 0x3)); + Q_ASSERT(!(reinterpret_cast(vPC) & 0x3)); return reinterpret_cast(reinterpret_cast(vPC) | (static_cast(inCTIFunction) << 1) | static_cast(inHostFunction)); } @@ -404,8 +404,8 @@ namespace JSC { fprintf(stderr, "DeletableSamplingCounter \"%s\" deleted early (with count %lld)\n", m_name, m_counter); // Our m_referer pointer should know where the pointer to this node is, // and m_next should know that this node is the previous node in the list. - ASSERT(*m_referer == this); - ASSERT(m_next->m_referer == &m_next); + Q_ASSERT(*m_referer == this); + Q_ASSERT(m_next->m_referer == &m_next); // Remove this node from the list, and inform m_next that we have done so. m_next->m_referer = m_referer; *m_referer = m_next; diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/bytecompiler/BytecodeGenerator.cpp b/src/3rdparty/javascriptcore/JavaScriptCore/bytecompiler/BytecodeGenerator.cpp index ee8181dbc..2dec0e2c9 100644 --- a/src/3rdparty/javascriptcore/JavaScriptCore/bytecompiler/BytecodeGenerator.cpp +++ b/src/3rdparty/javascriptcore/JavaScriptCore/bytecompiler/BytecodeGenerator.cpp @@ -463,10 +463,10 @@ bool BytecodeGenerator::willResolveToArguments(const Identifier& ident) RegisterID* BytecodeGenerator::uncheckedRegisterForArguments() { - ASSERT(willResolveToArguments(propertyNames().arguments)); + Q_ASSERT(willResolveToArguments(propertyNames().arguments)); SymbolTableEntry entry = symbolTable().get(propertyNames().arguments.ustring().rep()); - ASSERT(!entry.isNull()); + Q_ASSERT(!entry.isNull()); return ®isterFor(entry.getIndex()); } @@ -551,7 +551,7 @@ PassRefPtr