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3f190c55a4
Add socfpga_dtreg driver enablement for Intel SoCFPGA. Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024 Intel Corporation <www.intel.com>
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*/
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#define NUMBER_OF_ELEMENTS 3
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static int socfpga_dtreg_probe(struct udevice *dev)
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{
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const fdt32_t *list;
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fdt_addr_t offset, base;
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fdt_val_t val, read_val, mask, set_mask;
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int size, i;
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u32 blk_sz, reg;
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ofnode node;
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const char *name = NULL;
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debug("%s(dev=%p)\n", __func__, dev);
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if (!dev_has_ofnode(dev))
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return 0;
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dev_for_each_subnode(node, dev) {
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name = ofnode_get_name(node);
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if (!name)
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return -EINVAL;
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if (ofnode_read_u32_index(node, "reg", 1, &blk_sz))
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return -EINVAL;
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base = ofnode_get_addr(node);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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debug("%s(node_offset 0x%lx node_name %s ", __func__,
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node.of_offset, name);
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debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz);
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list = ofnode_read_prop(node, "intel,offset-settings", &size);
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if (!list)
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return -EINVAL;
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debug("%s(intel,offset-settings property size=%x)\n", __func__,
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size);
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size /= sizeof(*list) * NUMBER_OF_ELEMENTS;
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/*
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* First element: offset
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* Second element: val
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* Third element: mask
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*/
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for (i = 0; i < size; i++) {
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offset = fdt32_to_cpu(*list++);
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val = fdt32_to_cpu(*list++);
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/* Reads the masking bit value from the list */
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mask = fdt32_to_cpu(*list++);
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/*
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* Reads out the offsets, value and masking bits
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* Ex: <0x00000000 0x00000230 0xffffffff>
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*/
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debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n",
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__func__, offset, val, mask);
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if (blk_sz < offset + SZ_4) {
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printf("%s: Overflow as offset 0x%llx or reg",
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__func__, offset);
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printf(" write is more than block size 0x%x\n",
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blk_sz);
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return -EINVAL;
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}
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if (mask != 0) {
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if (mask == 0xffffffff) {
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reg = base + offset;
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writel(val, (uintptr_t)reg);
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} else {
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/* Mask the value with the masking bits */
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set_mask = val & mask;
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reg = base + offset;
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/* Clears and sets specific bits in the register */
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clrsetbits_le32((uintptr_t)reg, mask, set_mask);
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}
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}
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read_val = readl((uintptr_t)reg);
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/* Reads out the register, masked value and the read value */
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debug("%s(reg 0x%x = wr : 0x%llx rd : 0x%llx)\n",
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__func__, reg, set_mask, read_val);
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}
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}
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return 0;
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};
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static const struct udevice_id socfpga_dtreg_ids[] = {
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{.compatible = "intel,socfpga-dtreg"},
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{ }
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};
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U_BOOT_DRIVER(socfpga_dtreg) = {
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.name = "socfpga-dtreg",
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.id = UCLASS_NOP,
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.of_match = socfpga_dtreg_ids,
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.probe = socfpga_dtreg_probe,
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};
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