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386fca6896
This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
129 lines
3 KiB
C
129 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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static struct mm_region socfpga_agilex5_mem_map[] = {
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{
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/* OCRAM 512KB */
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x00080000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE,
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}, {
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/* DEVICE */
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.virt = 0x10808000UL,
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.phys = 0x10808000UL,
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.size = 0x0F7F8000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* FPGA 1.5GB */
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.virt = 0x20000000UL,
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.phys = 0x20000000UL,
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.size = 0x60000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* FPGA 15GB */
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.virt = 0x440000000UL,
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.phys = 0x440000000UL,
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.size = 0x3C0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* FPGA 240GB */
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.virt = 0x4400000000UL,
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.phys = 0x4400000000UL,
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.size = 0x3C00000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* MEM 2GB */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* List terminator */
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},
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};
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struct mm_region *mem_map = socfpga_agilex5_mem_map;
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#else
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static struct mm_region socfpga_stratix10_mem_map[] = {
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{
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/* MEM 2GB*/
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* FPGA 1.5GB */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x60000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* DEVICE 142MB */
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.virt = 0xF7000000UL,
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.phys = 0xF7000000UL,
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.size = 0x08E00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* OCRAM 1MB but available 256KB */
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.virt = 0xFFE00000UL,
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.phys = 0xFFE00000UL,
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.size = 0x00100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* DEVICE 32KB */
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.virt = 0xFFFC0000UL,
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.phys = 0xFFFC0000UL,
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.size = 0x00008000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* MEM 124GB */
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.virt = 0x0100000000UL,
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.phys = 0x0100000000UL,
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.size = 0x1F00000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* DEVICE 4GB */
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.virt = 0x2000000000UL,
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.phys = 0x2000000000UL,
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.size = 0x0100000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* List terminator */
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},
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};
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struct mm_region *mem_map = socfpga_stratix10_mem_map;
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#endif
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