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386fca6896
This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
124 lines
2.3 KiB
Text
124 lines
2.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2024 Intel Corporation <www.intel.com>
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*/
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#include "socfpga_agilex5-u-boot.dtsi"
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/{
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aliases {
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spi0 = &qspi;
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freeze_br0 = &freeze_controller;
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};
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soc {
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freeze_controller: freeze_controller@0x20000450 {
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compatible = "altr,freeze-bridge-controller";
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reg = <0x20000450 0x00000010>;
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status = "disabled";
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};
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};
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memory {
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/* 8GB */
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reg = <0 0x80000000 0 0x80000000>,
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<8 0x80000000 1 0x80000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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u-boot,spl-boot-order = &mmc,&flash0,"/memory";
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};
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};
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&flash0 {
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compatible = "jedec,spi-nor";
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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bootph-all;
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/delete-property/ cdns,read-delay;
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};
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&i3c0 {
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bootph-all;
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};
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&i3c1 {
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bootph-all;
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};
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&mmc {
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status = "okay";
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bus-width = <4>;
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sd-uhs-sdr50;
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cap-mmc-highspeed;
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bootph-all;
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};
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&combophy0 {
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status = "okay";
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bootph-all;
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cdns,phy-use-ext-lpbk-dqs = <1>;
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cdns,phy-use-lpbk-dqs = <1>;
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cdns,phy-use-phony-dqs = <1>;
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cdns,phy-use-phony-dqs-cmd = <1>;
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cdns,phy-io-mask-always-on = <0>;
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cdns,phy-io-mask-end = <5>;
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cdns,phy-io-mask-start = <0>;
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cdns,phy-data-select-oe-end = <1>;
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cdns,phy-sync-method = <1>;
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cdns,phy-sw-half-cycle-shift = <0>;
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cdns,phy-rd-del-sel = <52>;
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cdns,phy-underrun-suppress = <1>;
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cdns,phy-gate-cfg-always-on = <1>;
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cdns,phy-param-dll-bypass-mode = <1>;
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cdns,phy-param-phase-detect-sel = <2>;
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cdns,phy-param-dll-start-point = <254>;
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cdns,phy-read-dqs-cmd-delay = <0>;
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cdns,phy-clk-wrdqs-delay = <0>;
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cdns,phy-clk-wr-delay = <0>;
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cdns,phy-read-dqs-delay = <0>;
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cdns,phy-phony-dqs-timing = <0>;
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cdns,hrs09-rddata-en = <1>;
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cdns,hrs09-rdcmd-en = <1>;
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cdns,hrs09-extended-wr-mode = <1>;
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cdns,hrs09-extended-rd-mode = <1>;
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cdns,hrs10-hcsdclkadj = <3>;
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cdns,hrs16-wrdata1-sdclk-dly = <0>;
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cdns,hrs16-wrdata0-sdclk-dly = <0>;
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cdns,hrs16-wrcmd1-sdclk-dly = <0>;
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cdns,hrs16-wrcmd0-sdclk-dly = <0>;
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cdns,hrs16-wrdata1-dly = <0>;
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cdns,hrs16-wrdata0-dly = <0>;
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cdns,hrs16-wrcmd1-dly = <0>;
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cdns,hrs16-wrcmd0-dly = <0>;
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cdns,hrs07-rw-compensate = <10>;
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cdns,hrs07-idelay-val = <0>;
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};
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&qspi {
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status = "okay";
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};
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&timer0 {
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bootph-all;
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};
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&timer1 {
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bootph-all;
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};
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&timer2 {
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bootph-all;
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};
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&timer3 {
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bootph-all;
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};
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&watchdog0 {
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bootph-all;
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};
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