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a0186110af
Add missing parameters to support full configuration of the latest FSP MR6 release. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
307 lines
7.7 KiB
C
307 lines
7.7 KiB
C
/* SPDX-License-Identifier: Intel */
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright 2019 Google LLC
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*/
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#ifndef __ASM_ARCH_FSP_M_UDP_H
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#define __ASM_ARCH_FSP_M_UDP_H
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#ifndef __ASSEMBLY__
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#include <asm/fsp2/fsp_api.h>
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#define FSP_DRAM_CHANNELS 4
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struct __packed fspm_arch_upd {
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u8 revision;
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u8 reserved[3];
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void *nvs_buffer_ptr;
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void *stack_base;
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u32 stack_size;
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u32 boot_loader_tolum_size;
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u32 boot_mode;
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u8 reserved1[8];
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};
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struct __packed fsp_ram_channel {
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u8 rank_enable;
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u8 device_width;
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u8 dram_density;
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u8 option;
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u8 odt_config;
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u8 tristate_clk1;
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u8 mode2_n;
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u8 odt_levels;
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};
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/**
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* struct fsp_m_config - FSP-M configuration
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*
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* Note that headers precede this and are 64 bytes long. The hex offsets
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* mentioned in this file are relative to the start of the header, the same
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* convention used in Intel's APL FSP header file.
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*/
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struct __packed fsp_m_config {
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/* 0x40 */
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u32 serial_debug_port_address;
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u8 serial_debug_port_type;
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u8 serial_debug_port_device;
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u8 serial_debug_port_stride_size;
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u8 mrc_fast_boot;
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u8 igd;
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u8 igd_dvmt50_pre_alloc;
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u8 igd_aperture_size;
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u8 gtt_size;
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u8 primary_video_adaptor;
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u8 package;
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u8 profile;
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u8 memory_down;
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/* 0x50 */
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u8 ddr3_l_page_size;
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u8 ddr3_lasr;
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u8 scrambler_support;
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u8 interleaved_mode;
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u16 channel_hash_mask;
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u16 slice_hash_mask;
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u8 channels_slices_enable;
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u8 min_ref_rate2x_enable;
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u8 dual_rank_support_enable;
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u8 rmt_mode;
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u16 memory_size_limit;
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u16 low_memory_max_value;
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/* 0x60 */
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u16 high_memory_max_value;
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u8 disable_fast_boot;
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u8 dimm0_spd_address;
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u8 dimm1_spd_address;
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struct fsp_ram_channel chan[FSP_DRAM_CHANNELS];
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u8 rmt_check_run;
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u16 rmt_margin_check_scale_high_threshold;
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u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32];
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u32 msg_level_mask;
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u8 unused_upd_space0[4];
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/* 0x110 */
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u8 pre_mem_gpio_table_pin_num[4];
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u32 pre_mem_gpio_table_ptr;
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u8 pre_mem_gpio_table_entry_num;
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u8 enhance_port8xh_decoding;
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u8 spd_write_enable;
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u8 mrc_data_saving;
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u32 oem_loading_base;
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/* 0x120 */
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u8 oem_file_name[16];
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/* 0x130 */
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void *mrc_boot_data_ptr;
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u8 e_mmc_trace_len;
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u8 skip_cse_rbp;
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u8 npk_en;
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u8 fw_trace_en;
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u8 fw_trace_destination;
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u8 recover_dump;
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u8 msc0_wrap;
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u8 msc1_wrap;
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u32 msc0_size;
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/* 0x140 */
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u32 msc1_size;
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u8 pti_mode;
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u8 pti_training;
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u8 pti_speed;
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u8 punit_mlvl;
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u8 pmc_mlvl;
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u8 sw_trace_en;
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u8 periodic_retraining_disable;
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u8 enable_reset_system;
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u8 enable_s3_heci2;
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u8 unused_upd_space1[3];
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/* 0x150 */
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void *variable_nvs_buffer_ptr;
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u64 start_timer_ticker_of_pfet_assert;
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u8 rt_en;
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u8 skip_pcie_power_sequence;
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u8 reserved_fspm_upd[2];
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};
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/** FSP-M UPD Configuration */
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struct __packed fspm_upd {
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struct fsp_upd_header header;
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struct fspm_arch_upd arch;
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struct fsp_m_config config;
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u8 unused_upd_space2[158];
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u16 upd_terminator;
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};
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#endif
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#define SERIAL_DEBUG_PORT_TYPE_NONE 0
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#define SERIAL_DEBUG_PORT_TYPE_IO 1
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#define SERIAL_DEBUG_PORT_TYPE_MMIO 2
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#define SERIAL_DEBUG_PORT_DEVICE_UART0 0
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#define SERIAL_DEBUG_PORT_DEVICE_UART1 1
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#define SERIAL_DEBUG_PORT_DEVICE_UART2 2
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#define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3
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#define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0
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#define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2
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#define IGD_DVMT_50_PRE_ALLOC_64M 0x02
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#define IGD_DVMT_50_PRE_ALLOC_96M 0x03
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#define IGD_DVMT_50_PRE_ALLOC_128M 0x04
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#define IGD_DVMT_50_PRE_ALLOC_160M 0x05
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#define IGD_DVMT_50_PRE_ALLOC_192M 0x06
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#define IGD_DVMT_50_PRE_ALLOC_224M 0x07
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#define IGD_DVMT_50_PRE_ALLOC_256M 0x08
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#define IGD_DVMT_50_PRE_ALLOC_288M 0x09
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#define IGD_DVMT_50_PRE_ALLOC_320M 0x0a
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#define IGD_DVMT_50_PRE_ALLOC_352M 0x0b
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#define IGD_DVMT_50_PRE_ALLOC_384M 0x0c
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#define IGD_DVMT_50_PRE_ALLOC_416M 0x0d
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#define IGD_DVMT_50_PRE_ALLOC_448M 0x0e
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#define IGD_DVMT_50_PRE_ALLOC_480M 0x0f
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#define IGD_DVMT_50_PRE_ALLOC_512M 0x10
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#define IGD_APERTURE_SIZE_128M 0x1
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#define IGD_APERTURE_SIZE_256M 0x2
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#define IGD_APERTURE_SIZE_512M 0x3
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#define GTT_SIZE_2M 1
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#define GTT_SIZE_4M 2
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#define GTT_SIZE_8M 3
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#define PRIMARY_VIDEO_ADAPTER_AUTO 0
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#define PRIMARY_VIDEO_ADAPTER_IGD 2
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#define PRIMARY_VIDEO_ADAPTER_PCI 3
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#define PACKAGE_SODIMM 0
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#define PACKAGE_BGA 1
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#define PACKAGE_BGA_MIRRORED 2
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#define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3
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#define PROFILE_WIO2_800_7_8_8 0x1
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#define PROFILE_WIO2_1066_9_10_10 0x2
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#define PROFILE_LPDDR3_1066_8_10_10 0x3
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#define PROFILE_LPDDR3_1333_10_12_12 0x4
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#define PROFILE_LPDDR3_1600_12_15_15 0x5
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#define PROFILE_LPDDR3_1866_14_17_17 0x6
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#define PROFILE_LPDDR3_2133_16_20_20 0x7
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#define PROFILE_LPDDR4_1066_10_10_10 0x8
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#define PROFILE_LPDDR4_1600_14_15_15 0x9
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#define PROFILE_LPDDR4_2133_20_20_20 0xa
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#define PROFILE_LPDDR4_2400_24_22_22 0xb
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#define PROFILE_LPDDR4_2666_24_24_24 0xc
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#define PROFILE_LPDDR4_2933_28_27_27 0xd
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#define PROFILE_LPDDR4_3200_28_29_29 0xe
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#define PROFILE_DDR3_1066_6_6_6 0xf
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#define PROFILE_DDR3_1066_7_7_7 0x10
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#define PROFILE_DDR3_1066_8_8_8 0x11
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#define PROFILE_DDR3_1333_7_7_7 0x12
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#define PROFILE_DDR3_1333_8_8_8 0x13
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#define PROFILE_DDR3_1333_9_9_9 0x14
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#define PROFILE_DDR3_1333_10_10_10 0x15
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#define PROFILE_DDR3_1600_8_8_8 0x16
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#define PROFILE_DDR3_1600_9_9_9 0x17
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#define PROFILE_DDR3_1600_10_10_10 0x18
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#define PROFILE_DDR3_1600_11_11_11 0x19
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#define PROFILE_DDR3_1866_10_10_10 0x1a
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#define PROFILE_DDR3_1866_11_11_11 0x1b
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#define PROFILE_DDR3_1866_12_12_12 0x1c
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#define PROFILE_DDR3_1866_13_13_13 0x1d
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#define PROFILE_DDR3_2133_11_11_11 0x1e
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#define PROFILE_DDR3_2133_12_12_12 0x1f
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#define PROFILE_DDR3_2133_13_13_13 0x20
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#define PROFILE_DDR3_2133_14_14_14 0x21
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#define PROFILE_DDR4_1333_10_10_10 0x22
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#define PROFILE_DDR4_1600_10_10_10 0x23
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#define PROFILE_DDR4_1600_11_11_11 0x24
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#define PROFILE_DDR4_1600_12_12_12 0x25
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#define PROFILE_DDR4_1866_12_12_12 0x26
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#define PROFILE_DDR4_1866_13_13_13 0x27
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#define PROFILE_DDR4_1866_14_14_14 0x28
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#define PROFILE_DDR4_2133_14_14_14 0x29
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#define PROFILE_DDR4_2133_15_15_15 0x2a
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#define PROFILE_DDR4_2133_16_16_16 0x2b
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#define PROFILE_DDR4_2400_15_15_15 0x2c
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#define PROFILE_DDR4_2400_16_16_16 0x2d
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#define PROFILE_DDR4_2400_17_17_17 0x2e
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#define PROFILE_DDR4_2400_18_18_18 0x2f
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#define MEMORY_DOWN_NO 0
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#define MEMORY_DOWN_YES 1
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#define MEMORY_DOWN_MD_SODIMM 2
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#define MEMORY_DOWN_LPDDR4 3
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#define DDR3L_PAGE_SIZE_1KB 1
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#define DDR3L_PAGE_SIZE_2KB 2
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#define INTERLEAVED_MODE_DISABLE 0
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#define INTERLEAVED_MODE_ENABLE 2
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#define RMT_MODE_DISABLE 0
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#define RMT_MODE_ENABLE 3
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#define CHX_DEVICE_WIDTH_X8 0
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#define CHX_DEVICE_WIDTH_X16 1
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#define CHX_DEVICE_WIDTH_X32 2
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#define CHX_DEVICE_WIDTH_X64 3
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#define CHX_DEVICE_DENSITY_4GB 0
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#define CHX_DEVICE_DENSITY_6GB 1
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#define CHX_DEVICE_DENSITY_8GB 2
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#define CHX_DEVICE_DENSITY_12GB 3
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#define CHX_DEVICE_DENSITY_16GB 4
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#define CHX_DEVICE_DENSITY_2GB 5
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#define CHX_OPTION_RANK_INTERLEAVING 0x1
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#define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2
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#define CHX_OPTION_CH1_CLK_DISABLE 0x4
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#define CHX_OPTION_ADDRESS_MAP_2KB 0x10
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#define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1
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#define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2
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#define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10
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#define CHX_MODE2N_AUTO 0
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#define CHX_MODE2N_FORCE 1
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#define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0
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#define CHX_ODT_LEVELS_HELD_HIGH 0x1
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#define NPK_EN_DISABLE 0
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#define NPK_EN_ENABLE 1
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#define NPK_EN_DEBUGGER 2
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#define NPK_EN_AUTO 3
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#define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1
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#define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2
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#define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3
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#define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4
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#define MSC_X_WRAP_0 0
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#define MSC_X_WRAP_1 1
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#define MSC_X_SIZE_0M 0
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#define MSC_X_SIZE_1M 1
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#define MSC_X_SIZE_8M 2
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#define MSC_X_SIZE_64M 3
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#define MSC_X_SIZE_128M 4
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#define MSC_X_SIZE_256M 5
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#define MSC_X_SIZE_512M 6
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#define MSC_X_SIZE_1GB 7
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#define PTI_MODE_0 0
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#define PTI_MODE_x4 1
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#define PTI_MODE_x8 2
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#define PTI_MODE_x12 3
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#define PTI_MODE_x16 4
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#define PTI_SPEED_FULL 0
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#define PTI_SPEED_HALF 1
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#define PTI_SPEED_QUARTER 2
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#endif
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