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5f364e072e
Add clock controller driver for sophgo cv1800b SoC Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
74 lines
1.7 KiB
C
74 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
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*
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*/
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#ifndef __CLK_SOPHGO_COMMON_H__
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#define __CLK_SOPHGO_COMMON_H__
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#include <linux/bitops.h>
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#include <linux/io.h>
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#define CV1800B_CLK_OSC 1
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#define CV1800B_CLK_BYPASS 2
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#define CV1800B_CLK_ID_TRANSFORM(_id) ((_id) + 3)
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struct cv1800b_clk_regbit {
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u32 offset;
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u8 shift;
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};
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struct cv1800b_clk_regfield {
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u32 offset;
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u8 shift;
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u8 width;
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};
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#define CV1800B_CLK_REGBIT(_offset, _shift) \
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{ \
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.offset = _offset, \
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.shift = _shift, \
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}
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#define CV1800B_CLK_REGFIELD(_offset, _shift, _width) \
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{ \
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.offset = _offset, \
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.shift = _shift, \
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.width = _width, \
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}
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static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit *bit)
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{
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return readl(base + bit->offset) & (BIT(bit->shift));
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}
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static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit *bit)
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{
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return setbits_le32(base + bit->offset, BIT(bit->shift));
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}
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static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit *bit)
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{
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return clrbits_le32(base + bit->offset, BIT(bit->shift));
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}
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static inline u32 cv1800b_clk_getfield(void *base,
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struct cv1800b_clk_regfield *field)
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{
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u32 mask = GENMASK(field->shift + field->width - 1, field->shift);
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return (readl(base + field->offset) & mask) >> field->shift;
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}
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static inline void
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cv1800b_clk_setfield(void *base, struct cv1800b_clk_regfield *field, u32 val)
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{
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u32 mask = GENMASK(field->shift + field->width - 1, field->shift);
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u32 new_val = (readl(base + field->offset) & ~mask) |
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((val << field->shift) & mask);
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return writel(new_val, base + field->offset);
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}
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#endif /* __CLK_SOPHGO_COMMON_H__ */
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