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92659829aa
The R-Car V4H SPL implementation was originally running on the Cortex-R52
core, but this is no longer the case. Majority of the SPL now runs on the
Cortex-A76 core. Drop the stale description.
Fixes: ec53fdee5b ("arm64: renesas: Add Renesas R-Car V4H SPL implementation")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
102 lines
2.1 KiB
C
102 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R-Car Gen4 SPL
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*
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* Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*/
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#include <asm/arch/renesas.h>
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#include <asm/io.h>
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#include <cpu_func.h>
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#include <dm/uclass.h>
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#include <dm/util.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <linux/bitops.h>
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#include <log.h>
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#include <mapmem.h>
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#include <spl.h>
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#define CNTCR_EN BIT(0)
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#ifdef CONFIG_SPL_BUILD
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void board_debug_uart_init(void)
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{
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}
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#endif
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static void init_generic_timer(void)
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{
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const u32 freq = CONFIG_SYS_CLK_FREQ;
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/* Update memory mapped and register based freqency */
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if (IS_ENABLED(CONFIG_ARM64))
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asm volatile("msr cntfrq_el0, %0" :: "r" (freq));
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else
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asm volatile("mcr p15, 0, %0, c14, c0, 0" :: "r" (freq));
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writel(freq, CNTFID0);
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/* Enable counter */
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setbits_le32(CNTCR_BASE, CNTCR_EN);
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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if (CONFIG_IS_ENABLED(OF_CONTROL)) {
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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}
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preloader_console_init();
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ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e6780000", &dev);
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if (ret)
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printf("DBSC5 init failed: %d\n", ret);
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ret = uclass_get_device_by_name(UCLASS_RAM, "ram@ffec0000", &dev);
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if (ret)
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printf("RTVRAM init failed: %d\n", ret);
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};
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_SPI;
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}
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struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
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{
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return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0);
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}
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#define APMU_BASE 0xe6170000U
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#define CL0GRP3_BIT BIT(3)
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#define CL1GRP3_BIT BIT(7)
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#define RTGRP3_BIT BIT(19)
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#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
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void s_init(void)
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{
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/* Unlock CPG access */
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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init_generic_timer();
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/* Define for Work Around of APMU */
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writel(0x00ff00ff, APMU_BASE + 0x10);
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writel(0x00ff00ff, APMU_BASE + 0x14);
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writel(0x00ff00ff, APMU_BASE + 0x18);
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writel(0x00ff00ff, APMU_BASE + 0x1c);
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clrbits_le32(APMU_BASE + 0x68, BIT(29));
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}
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void reset_cpu(void)
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{
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}
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