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db5741f7a8
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
124 lines
4.3 KiB
C
124 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _SYSTEM_MANAGER_S10_
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#define _SYSTEM_MANAGER_S10_
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void sysmgr_pinmux_init(void);
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void populate_sysmgr_fpgaintf_module(void);
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void populate_sysmgr_pinmux(void);
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void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
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#define SYSMGR_S10_WDDBG 0x08
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#define SYSMGR_S10_DMA 0x20
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#define SYSMGR_S10_DMA_PERIPH 0x24
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#define SYSMGR_S10_SDMMC 0x28
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#define SYSMGR_S10_SDMMC_L3MASTER 0x2c
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#define SYSMGR_S10_EMAC_GLOBAL 0x40
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#define SYSMGR_S10_EMAC0 0x44
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#define SYSMGR_S10_EMAC1 0x48
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#define SYSMGR_S10_EMAC2 0x4c
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#define SYSMGR_S10_EMAC0_ACE 0x50
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#define SYSMGR_S10_EMAC1_ACE 0x54
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#define SYSMGR_S10_EMAC2_ACE 0x58
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#define SYSMGR_S10_NAND_AXUSER 0x5c
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#define SYSMGR_S10_FPGAINTF_EN1 0x68
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#define SYSMGR_S10_FPGAINTF_EN2 0x6c
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#define SYSMGR_S10_FPGAINTF_EN3 0x70
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#define SYSMGR_S10_DMA_L3MASTER 0x74
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#define SYSMGR_S10_HMC_CLK 0xb4
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#define SYSMGR_S10_IO_PA_CTRL 0xb8
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#define SYSMGR_S10_NOC_TIMEOUT 0xc0
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#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4
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#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8
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#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc
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#define SYSMGR_S10_NOC_IDLEACK 0xd0
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#define SYSMGR_S10_NOC_IDLESTATUS 0xd4
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#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8
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#define SYSMGR_S10_FPGA_CONFIG 0xdc
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#define SYSMGR_S10_IOCSRCLK_GATE 0xe0
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#define SYSMGR_S10_GPO 0xe4
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#define SYSMGR_S10_GPI 0xe8
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#define SYSMGR_S10_MPU 0xf0
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#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200
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#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204
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#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208
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#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c
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#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210
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#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214
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#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218
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#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c
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#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220
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#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224
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#define SYSMGR_S10_PINSEL0 0x1000
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#define SYSMGR_S10_IOCTRL0 0x1130
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#define SYSMGR_S10_EMAC0_USEFPGA 0x1300
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#define SYSMGR_S10_EMAC1_USEFPGA 0x1304
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#define SYSMGR_S10_EMAC2_USEFPGA 0x1308
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#define SYSMGR_S10_I2C0_USEFPGA 0x130c
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#define SYSMGR_S10_I2C1_USEFPGA 0x1310
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#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314
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#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318
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#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c
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#define SYSMGR_S10_NAND_USEFPGA 0x1320
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#define SYSMGR_S10_SPIM0_USEFPGA 0x1328
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#define SYSMGR_S10_SPIM1_USEFPGA 0x132c
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#define SYSMGR_S10_SPIS0_USEFPGA 0x1330
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#define SYSMGR_S10_SPIS1_USEFPGA 0x1334
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#define SYSMGR_S10_UART0_USEFPGA 0x1338
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#define SYSMGR_S10_UART1_USEFPGA 0x133c
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#define SYSMGR_S10_MDIO0_USEFPGA 0x1340
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#define SYSMGR_S10_MDIO1_USEFPGA 0x1344
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#define SYSMGR_S10_MDIO2_USEFPGA 0x1348
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#define SYSMGR_S10_JTAG_USEFPGA 0x1350
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#define SYSMGR_S10_SDMMC_USEFPGA 0x1354
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#define SYSMGR_S10_HPS_OSC_CLK 0x1358
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#define SYSMGR_S10_IODELAY0 0x1400
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#define SYSMGR_SDMMC SYSMGR_S10_SDMMC
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
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#define SYSMGR_ECC_OCRAM_EN BIT(0)
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#define SYSMGR_ECC_OCRAM_SERR BIT(3)
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#define SYSMGR_ECC_OCRAM_DERR BIT(4)
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#define SYSMGR_FPGAINTF_USEFPGA 0x1
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#define SYSMGR_FPGAINTF_NAND BIT(4)
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#define SYSMGR_FPGAINTF_SDMMC BIT(8)
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#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
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#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
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#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
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#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
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#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
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#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
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/* EMAC Group Bit definitions */
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
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#define SYSMGR_NOC_H2F_MSK 0x00000001
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#define SYSMGR_NOC_LWH2F_MSK 0x00000010
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#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
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#define SYSMGR_DMA_IRQ_NS 0xFF000000
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#define SYSMGR_DMA_MGR_NS 0x00010000
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#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
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#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
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#endif /* _SYSTEM_MANAGER_S10_ */
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