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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
119 lines
2.7 KiB
C
119 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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* Copyright (C) 2018, Anup Patel <anup@brainfault.org>
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* Copyright (C) 2012 Regents of the University of California
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*
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* RISC-V architecturally-defined generic timer driver
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*
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* This driver provides generic timer support for S-mode U-Boot.
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*/
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <timer.h>
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#include <asm/csr.h>
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static u64 notrace riscv_timer_get_count(struct udevice *dev)
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{
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__maybe_unused u32 hi, lo;
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if (IS_ENABLED(CONFIG_64BIT))
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return csr_read(CSR_TIME);
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do {
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hi = csr_read(CSR_TIMEH);
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lo = csr_read(CSR_TIME);
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} while (hi != csr_read(CSR_TIMEH));
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return ((u64)hi << 32) | lo;
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}
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#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
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/**
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* timer_early_get_rate() - Get the timer rate before driver model
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*/
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unsigned long notrace timer_early_get_rate(void)
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{
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return RISCV_SMODE_TIMER_FREQ;
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}
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/**
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* timer_early_get_count() - Get the timer count before driver model
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*
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*/
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u64 notrace timer_early_get_count(void)
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{
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return riscv_timer_get_count(NULL);
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}
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#endif
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#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
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ulong timer_get_boot_us(void)
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{
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int ret;
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u64 ticks = 0;
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u32 rate;
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ret = dm_timer_init();
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if (!ret) {
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rate = timer_get_rate(gd->timer);
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timer_get_count(gd->timer, &ticks);
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} else {
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rate = RISCV_SMODE_TIMER_FREQ;
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ticks = riscv_timer_get_count(NULL);
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}
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/* Below is converted from time(us) = (tick / rate) * 10000000 */
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return lldiv(ticks * 1000, (rate / 1000));
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}
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#endif
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static int riscv_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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u32 rate;
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/* When this function was called from the CPU driver, clock
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* frequency is passed as driver data.
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*/
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rate = dev->driver_data;
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/* When called from an FDT match, the rate needs to be looked up. */
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if (!rate && gd->fdt_blob) {
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rate = fdt_getprop_u32_default(gd->fdt_blob,
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"/cpus", "timebase-frequency", 0);
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}
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uc_priv->clock_rate = rate;
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/* With rate==0, timer uclass post_probe might later fail with -EINVAL.
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* Give a hint at the cause for debugging.
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*/
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if (!rate)
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log_err("riscv_timer_probe with invalid clock rate 0!\n");
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return 0;
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}
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static const struct timer_ops riscv_timer_ops = {
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.get_count = riscv_timer_get_count,
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};
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static const struct udevice_id riscv_timer_ids[] = {
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{ .compatible = "riscv,timer", },
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{ }
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};
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U_BOOT_DRIVER(riscv_timer) = {
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.name = "riscv_timer",
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.id = UCLASS_TIMER,
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.of_match = of_match_ptr(riscv_timer_ids),
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.probe = riscv_timer_probe,
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.ops = &riscv_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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