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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
115 lines
2.9 KiB
C
115 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#define NPCM_TIMER_CLOCK_RATE 1000000UL /* 1MHz timer */
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#define NPCM_TIMER_INPUT_RATE 25000000UL /* Rate of input clock */
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#define NPCM_TIMER_TDR_MASK GENMASK(23, 0)
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#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
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/* Register offsets */
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#define TCR0 0x0 /* Timer Control and Status Register */
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#define TICR0 0x8 /* Timer Initial Count Register */
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#define TDR0 0x10 /* Timer Data Register */
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/* TCR fields */
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#define TCR_MODE_PERIODIC BIT(27)
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#define TCR_EN BIT(30)
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#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE - 1)
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enum input_clock_type {
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INPUT_CLOCK_FIXED, /* input clock rate is fixed */
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INPUT_CLOCK_NON_FIXED
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};
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/**
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* struct npcm_timer_priv - private data for npcm timer driver
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* npcm timer is a 24-bits down-counting timer.
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*
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* @last_count: last hw counter value
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* @counter: the value to be returned for get_count ops
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*/
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struct npcm_timer_priv {
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void __iomem *base;
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u32 last_count;
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u64 counter;
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};
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static u64 npcm_timer_get_count(struct udevice *dev)
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{
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struct npcm_timer_priv *priv = dev_get_priv(dev);
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u32 val;
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/* The timer is counting down */
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val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
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if (val <= priv->last_count)
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priv->counter += priv->last_count - val;
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else
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priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 - val);
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priv->last_count = val;
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return priv->counter;
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}
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static int npcm_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct npcm_timer_priv *priv = dev_get_priv(dev);
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enum input_clock_type type = dev_get_driver_data(dev);
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struct clk clk;
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
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if (type == INPUT_CLOCK_NON_FIXED) {
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
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if (ret < 0)
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return ret;
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}
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/*
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* Configure timer and start
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* periodic mode
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* timer clock rate = input clock / prescale
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*/
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writel(0, priv->base + TCR0);
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writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
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writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
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priv->base + TCR0);
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return 0;
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}
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static const struct timer_ops npcm_timer_ops = {
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.get_count = npcm_timer_get_count,
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};
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static const struct udevice_id npcm_timer_ids[] = {
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{ .compatible = "nuvoton,npcm845-timer", .data = INPUT_CLOCK_FIXED},
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{ .compatible = "nuvoton,npcm750-timer", .data = INPUT_CLOCK_NON_FIXED},
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{}
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};
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U_BOOT_DRIVER(npcm_timer) = {
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.name = "npcm_timer",
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.id = UCLASS_TIMER,
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.of_match = npcm_timer_ids,
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.priv_auto = sizeof(struct npcm_timer_priv),
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.probe = npcm_timer_probe,
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.ops = &npcm_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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