mirror of
https://github.com/u-boot/u-boot.git
synced 2025-05-07 04:39:20 +00:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
37 lines
1.1 KiB
C
37 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2013-2024 Altera Corporation <www.altera.com>
|
|
*/
|
|
|
|
#ifndef _CLOCK_MANAGER_H_
|
|
#define _CLOCK_MANAGER_H_
|
|
|
|
phys_addr_t socfpga_get_clkmgr_addr(void);
|
|
|
|
#ifndef __ASSEMBLY__
|
|
void cm_wait_for_lock(u32 mask);
|
|
int cm_wait_for_fsm(void);
|
|
void cm_print_clock_quick_summary(void);
|
|
unsigned long cm_get_mpu_clk_hz(void);
|
|
unsigned int cm_get_qspi_controller_clk_hz(void);
|
|
|
|
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
|
|
int cm_set_qspi_controller_clk_hz(u32 clk_hz);
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
|
|
#include <asm/arch/clock_manager_gen5.h>
|
|
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
|
|
#include <asm/arch/clock_manager_arria10.h>
|
|
#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
|
|
#include <asm/arch/clock_manager_s10.h>
|
|
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
|
|
#include <asm/arch/clock_manager_agilex.h>
|
|
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
|
|
#include <asm/arch/clock_manager_agilex5.h>
|
|
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
|
|
#include <asm/arch/clock_manager_n5x.h>
|
|
#endif
|
|
|
|
#endif /* _CLOCK_MANAGER_H_ */
|