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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
130 lines
2.8 KiB
C
130 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include "fsl_ls1_serdes.h"
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#ifdef CONFIG_SYS_FSL_SRDS_1
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static u64 serdes1_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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static u64 serdes2_prtcl_map;
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#endif
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int is_serdes_configured(enum srds_prtcl device)
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{
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u64 ret = 0;
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#ifdef CONFIG_SYS_FSL_SRDS_1
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if (!(serdes1_prtcl_map & (1ULL << NONE)))
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fsl_serdes_init();
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ret |= (1ULL << device) & serdes1_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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if (!(serdes2_prtcl_map & (1ULL << NONE)))
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fsl_serdes_init();
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ret |= (1ULL << device) & serdes2_prtcl_map;
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#endif
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return !!ret;
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}
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
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{
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
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u32 cfg = in_be32(&gur->rcwsr[4]);
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int i;
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switch (sd) {
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#ifdef CONFIG_SYS_FSL_SRDS_1
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case FSL_SRDS_1:
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cfg &= RCWSR4_SRDS1_PRTCL_MASK;
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cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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case FSL_SRDS_2:
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cfg &= RCWSR4_SRDS2_PRTCL_MASK;
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cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
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break;
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#endif
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default:
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printf("invalid SerDes%d\n", sd);
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break;
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}
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/* Is serdes enabled at all? */
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if (unlikely(cfg == 0))
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return -ENODEV;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_get_prtcl(sd, cfg, i) == device)
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return i;
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}
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return -ENODEV;
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}
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u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
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{
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
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u64 serdes_prtcl_map = 0;
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u32 cfg;
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int lane;
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cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
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cfg >>= sd_prctl_shift;
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printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
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if (!is_serdes_prtcl_valid(sd, cfg))
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printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
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serdes_prtcl_map |= (1ULL << lane_prtcl);
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}
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/* Set the first bit to indicate serdes has been initialized */
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serdes_prtcl_map |= (1ULL << NONE);
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return serdes_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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#ifdef CONFIG_SYS_FSL_SRDS_1
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if (!(serdes1_prtcl_map & (1ULL << NONE)))
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serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
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CFG_SYS_FSL_SERDES_ADDR,
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RCWSR4_SRDS1_PRTCL_MASK,
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RCWSR4_SRDS1_PRTCL_SHIFT);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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if (!(serdes2_prtcl_map & (1ULL << NONE)))
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serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
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CFG_SYS_FSL_SERDES_ADDR +
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FSL_SRDS_2 * 0x1000,
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RCWSR4_SRDS2_PRTCL_MASK,
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RCWSR4_SRDS2_PRTCL_SHIFT);
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#endif
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}
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const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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default:
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return "100";
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}
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}
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