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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
118 lines
2.6 KiB
C
118 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <fsl_ifc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void get_sys_info(struct sys_info *sys_info)
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{
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
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struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
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unsigned int cpu;
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const u8 core_cplx_pll[6] = {
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[0] = 0, /* CC1 PPL / 1 */
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[1] = 0, /* CC1 PPL / 2 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 1, /* CC2 PPL / 2 */
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};
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const u8 core_cplx_pll_div[6] = {
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[0] = 1, /* CC1 PPL / 1 */
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[1] = 2, /* CC1 PPL / 2 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 2, /* CC2 PPL / 2 */
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};
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uint i;
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uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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unsigned long sysclk = get_board_sys_clk();
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sys_info->freq_systembus = sysclk;
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#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
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sys_info->freq_ddrbus = get_board_ddr_clk();
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#else
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sys_info->freq_ddrbus = sysclk;
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#endif
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sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >>
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RCWSR0_SYS_PLL_RAT_SHIFT) & RCWSR0_SYS_PLL_RAT_MASK;
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sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >>
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RCWSR0_MEM_PLL_RAT_SHIFT) & RCWSR0_MEM_PLL_RAT_MASK;
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
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if (ratio[i] > 4)
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freq_c_pll[i] = sysclk * ratio[i];
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else
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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}
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for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
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u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
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& 0xf;
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u32 cplx_pll = core_cplx_pll[c_pll_sel];
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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#if defined(CONFIG_FSL_IFC)
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sys_info->freq_localbus = sys_info->freq_systembus;
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#endif
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}
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int get_clocks(void)
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{
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struct sys_info sys_info;
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get_sys_info(&sys_info);
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus;
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gd->mem_clk = sys_info.freq_ddrbus * 2;
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#if defined(CONFIG_FSL_ESDHC)
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gd->arch.sdhc_clk = gd->bus_clk;
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#endif
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return 0;
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}
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ulong get_bus_freq(ulong dummy)
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{
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return gd->bus_clk;
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}
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ulong get_ddr_freq(ulong dummy)
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{
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return gd->mem_clk;
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}
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int get_serial_clock(void)
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{
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return gd->bus_clk / 2;
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_I2C_CLK:
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return get_bus_freq(0) / 2;
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case MXC_DSPI_CLK:
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return get_bus_freq(0) / 2;
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case MXC_UART_CLK:
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return get_bus_freq(0) / 2;
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default:
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printf("Unsupported clock\n");
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}
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return 0;
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}
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