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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
132 lines
3.1 KiB
C
132 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Broadcom Corporation.
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*/
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#include <common.h>
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#include <div64.h>
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#include <init.h>
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#include <time.h>
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#include <asm/io.h>
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#include <asm/iproc-common/timer.h>
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#include <asm/iproc-common/sysmap.h>
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#include <linux/delay.h>
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static inline uint64_t timer_global_read(void)
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{
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uint64_t cur_tick;
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uint32_t count_h;
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uint32_t count_l;
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do {
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count_h = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
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TIMER_GLB_HI_OFFSET);
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count_l = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
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TIMER_GLB_LOW_OFFSET);
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cur_tick = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
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TIMER_GLB_HI_OFFSET);
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} while (cur_tick != count_h);
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return (cur_tick << 32) + count_l;
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}
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void timer_global_init(void)
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{
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writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
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writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_LOW_OFFSET);
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writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_HI_OFFSET);
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writel(TIMER_GLB_TIM_CTRL_TIM_EN,
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IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
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}
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int timer_init(void)
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{
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timer_global_init();
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return 0;
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}
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unsigned long get_timer(unsigned long base)
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{
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uint64_t count;
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uint64_t ret;
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uint64_t tim_clk;
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uint64_t periph_clk;
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count = timer_global_read();
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/* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per msec */
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periph_clk = 500000;
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tim_clk = lldiv(periph_clk,
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(((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
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TIMER_GLB_CTRL_OFFSET) &
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TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
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ret = lldiv(count, (uint32_t)tim_clk);
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/* returns msec */
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return ret - base;
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}
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void __udelay(unsigned long usec)
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{
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uint64_t cur_tick, end_tick;
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uint64_t tim_clk;
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uint64_t periph_clk;
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/* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec */
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periph_clk = 500;
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tim_clk = lldiv(periph_clk,
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(((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
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TIMER_GLB_CTRL_OFFSET) &
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TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
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cur_tick = timer_global_read();
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end_tick = tim_clk;
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end_tick *= usec;
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end_tick += cur_tick;
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do {
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cur_tick = timer_global_read();
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} while (cur_tick < end_tick);
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}
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void timer_systick_init(uint32_t tick_ms)
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{
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/* Disable timer and clear interrupt status*/
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writel(0, IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
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writel(TIMER_PVT_TIM_INT_STATUS_SET,
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IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
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writel((PLL_AXI_CLK/1000) * tick_ms,
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IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_LOAD_OFFSET);
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writel(TIMER_PVT_TIM_CTRL_INT_EN |
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TIMER_PVT_TIM_CTRL_AUTO_RELD |
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TIMER_PVT_TIM_CTRL_TIM_EN,
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IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
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}
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void timer_systick_isr(void *data)
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{
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writel(TIMER_PVT_TIM_INT_STATUS_SET,
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IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value in msec.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This is used in conjuction with get_ticks, which returns msec as ticks.
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* Here we just return ticks/sec = msec/sec = 1000
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*/
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ulong get_tbclk(void)
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{
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return 1000;
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}
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