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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
90 lines
1.9 KiB
C
90 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <irq_func.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <asm/armv7.h>
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#include <linux/compiler.h>
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void __weak cpu_cache_initialization(void){}
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int cleanup_before_linux_select(int flags)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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*/
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#ifndef CONFIG_SPL_BUILD
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disable_interrupts();
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#endif
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if (flags & CBL_DISABLE_CACHES) {
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/*
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* turn off D-cache
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* dcache_disable() in turn flushes the d-cache and disables MMU
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*/
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dcache_disable();
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v7_outer_cache_disable();
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/*
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* After D-cache is flushed and before it is disabled there may
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* be some new valid entries brought into the cache. We are
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* sure that these lines are not dirty and will not affect our
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* execution. (because unwinding the call-stack and setting a
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* bit in CP15 SCTRL is all we did during this. We have not
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* pushed anything on to the stack. Neither have we affected
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* any static data) So just invalidate the entire d-cache again
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* to avoid coherency problems for kernel
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*/
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invalidate_dcache_all();
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icache_disable();
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invalidate_icache_all();
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} else {
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/*
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* Turn off I-cache and invalidate it
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*/
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icache_disable();
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invalidate_icache_all();
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flush_dcache_all();
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invalidate_icache_all();
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icache_enable();
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}
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/*
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* Some CPU need more cache attention before starting the kernel.
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*/
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cpu_cache_initialization();
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return 0;
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}
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int cleanup_before_linux(void)
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{
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return cleanup_before_linux_select(CBL_ALL);
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}
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void allow_unaligned(void)
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{
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v7_arch_cp15_allow_unaligned();
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}
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