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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
119 lines
2.4 KiB
C
119 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2004 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <irq_func.h>
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <asm/arm11.h>
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static void cache_flush(void);
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int cleanup_before_linux (void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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*/
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disable_interrupts();
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/* turn off I/D-cache */
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icache_disable();
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dcache_disable();
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/* flush I/D-cache */
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cache_flush();
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return 0;
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}
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void allow_unaligned(void)
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{
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arm11_arch_cp15_allow_unaligned();
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}
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static void cache_flush(void)
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{
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unsigned long i = 0;
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/* clean entire data cache */
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asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
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/* invalidate both caches and flush btb */
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asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
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/* mem barrier to sync things */
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void invalidate_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
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}
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void flush_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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}
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#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
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#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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void enable_caches(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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icache_enable();
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#endif
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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dcache_enable();
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#endif
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}
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#endif
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