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d22fe8f2aa
Add support for the PCIe QMP PHY on the SM8550, SM8650 and x1e80100 SoCs. The driver is based on the Linux phy/qualcomm/phy-qcom-qmp-pcie.c driver and adapted to U-Boot. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-phy-v1-1-bf08811d0a07@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
32 lines
1.4 KiB
C
32 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
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#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
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#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
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#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
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#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
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#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
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#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
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#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
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#endif
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