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d22fe8f2aa
Add support for the PCIe QMP PHY on the SM8550, SM8650 and x1e80100 SoCs. The driver is based on the Linux phy/qualcomm/phy-qcom-qmp-pcie.c driver and adapted to U-Boot. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-phy-v1-1-bf08811d0a07@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
34 lines
1.2 KiB
C
34 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V5_H_
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#define QCOM_PHY_QMP_PCS_V5_H_
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/* Only for QMP V5 PHY - USB/PCIe PCS registers */
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#define QPHY_V5_PCS_SW_RESET 0x000
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#define QPHY_V5_PCS_PCS_STATUS1 0x014
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#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
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#define QPHY_V5_PCS_START_CONTROL 0x044
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#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
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#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
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#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
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#define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
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#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
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#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V5_PCS_CDR_RESET_TIME 0x1b0
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#define QPHY_V5_PCS_RX_CONFIG 0x1b0
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#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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#define QPHY_V5_PCS_PCS_TX_RX_CONFIG 0x1d0
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#define QPHY_V5_PCS_EQ_CONFIG1 0x1dc
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#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
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#define QPHY_V5_PCS_EQ_CONFIG5 0x1ec
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#endif
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