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d22fe8f2aa
Add support for the PCIe QMP PHY on the SM8550, SM8650 and x1e80100 SoCs. The driver is based on the Linux phy/qualcomm/phy-qcom-qmp-pcie.c driver and adapted to U-Boot. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-phy-v1-1-bf08811d0a07@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
23 lines
871 B
C
23 lines
871 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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/* Only for QMP V5_20 PHY - PCIe PCS registers */
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#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
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#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
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#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
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#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
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#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24
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#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28
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#endif
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