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cff38c5504
There is no need for assembly in the platform specific part of the PSCI implementation. Note that this does not make it a complete PSCI 1.0 implementation yet but aids to do so in upcoming patches. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
123 lines
2.7 KiB
C
123 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <asm/arch/imx-regs.h>
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#include <common.h>
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#include <fsl_wdog.h>
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#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
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#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
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#define GPC_PGC_C1 0x840
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#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
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/* below is for i.MX7D */
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#define SRC_GPR1_MX7D 0x074
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#define SRC_A7RCR0 0x004
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#define SRC_A7RCR1 0x008
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#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
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#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
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#define SNVS_LPCR 0x38
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#define BP_SNVS_LPCR_DP_EN 0x20
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#define BP_SNVS_LPCR_TOP 0x40
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#define CCM_CCGR_SNVS 0x4250
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#define CCM_ROOT_WDOG 0xbb80
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#define CCM_CCGR_WDOG1 0x49c0
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static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
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{
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writel(enable, GPC_IPS_BASE_ADDR + offset);
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}
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__secure void imx_gpcv2_set_core1_power(bool pdn)
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{
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u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
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u32 val;
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imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
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val = readl(GPC_IPS_BASE_ADDR + reg);
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val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
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writel(val, GPC_IPS_BASE_ADDR + reg);
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while ((readl(GPC_IPS_BASE_ADDR + reg) &
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BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
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;
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imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
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}
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__secure void imx_enable_cpu_ca7(int cpu, bool enable)
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{
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u32 mask, val;
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mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
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val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
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val = enable ? val | mask : val & ~mask;
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writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
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}
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__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep,
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u32 context_id)
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{
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u32 cpu = (mpidr & 0x1);
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psci_save(cpu, ep, context_id);
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writel((u32)psci_cpu_entry, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
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imx_gpcv2_set_core1_power(true);
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imx_enable_cpu_ca7(cpu, true);
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return 0;
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}
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__secure s32 psci_cpu_off(void)
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{
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int cpu;
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psci_cpu_off_common();
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cpu = psci_get_cpu_id();
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imx_enable_cpu_ca7(cpu, false);
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imx_gpcv2_set_core1_power(false);
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writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
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while (1)
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wfi();
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}
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__secure void psci_system_reset(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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/* make sure WDOG1 clock is enabled */
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writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
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writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
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writew(WCR_WDE, &wdog->wcr);
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while (1)
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wfi();
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}
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__secure void psci_system_off(void)
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{
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u32 val;
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/* make sure SNVS clock is enabled */
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writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
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val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
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val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
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writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
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while (1)
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wfi();
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}
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