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cae6e8993c
Import DDR training code from commit 1b69ce2fc0 ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_IP_BIST_H_
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#define _DDR3_TRAINING_IP_BIST_H_
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#include "ddr3_training_ip.h"
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enum hws_bist_operation {
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BIST_STOP = 0,
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BIST_START = 1
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};
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enum hws_stress_jump {
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STRESS_NONE = 0,
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STRESS_ENABLE = 1
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};
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enum hws_pattern_duration {
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DURATION_SINGLE = 0,
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DURATION_STOP_AT_FAIL = 1,
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DURATION_ADDRESS = 2,
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DURATION_CONT = 4
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};
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struct bist_result {
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u32 bist_error_cnt;
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u32 bist_fail_low;
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u32 bist_fail_high;
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u32 bist_last_fail_addr;
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};
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int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
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struct bist_result *pst_bist_result);
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int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
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enum hws_access_type access_type,
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u32 if_num, enum hws_dir direction,
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enum hws_stress_jump addr_stress_jump,
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enum hws_pattern_duration duration,
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enum hws_bist_operation oper_type,
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u32 offset, u32 cs_num, u32 pattern_addr_length);
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int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
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u32 cs_num);
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int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
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u32 mode);
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int ddr3_tip_print_regs(u32 dev_num);
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int ddr3_tip_reg_dump(u32 dev_num);
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int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
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u32 burst_length);
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#endif /* _DDR3_TRAINING_IP_BIST_H_ */
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