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cae6e8993c
Import DDR training code from commit 1b69ce2fc0 ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_HWS_HW_TRAINING_H
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#define _DDR3_HWS_HW_TRAINING_H
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/* struct used for DLB configuration array */
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struct dlb_config {
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u32 reg_addr;
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u32 reg_data;
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};
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/* Topology update structure */
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struct topology_update_info {
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int update_ecc;
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u8 ecc;
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int update_width;
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u8 width;
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int update_ecc_pup3_mode;
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u8 ecc_pup_mode_offset;
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};
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/* Topology update defines */
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#define TOPOLOGY_UPDATE_WIDTH_16BIT 1
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#define TOPOLOGY_UPDATE_WIDTH_32BIT 0
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#define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK 0xf
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#define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK 0x3
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#define TOPOLOGY_UPDATE_ECC_ON 1
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#define TOPOLOGY_UPDATE_ECC_OFF 0
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#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4 4
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#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3 3
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/*
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* 1. L2 filter should be set at binary header to 0xd000000,
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* to avoid conflict with internal register IO.
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* 2. U-Boot modifies internal registers base to 0xf100000,
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* and than should update L2 filter accordingly to 0xf000000 (3.75 GB)
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*/
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/* temporary limit l2 filter to 3GiB (LSP issue) */
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#define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000
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#define ADDRESS_FILTERING_END_REGISTER 0x8c04
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#define SUB_VERSION 0
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#endif /* _DDR3_HWS_HW_TRAINING_H */
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