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cae6e8993c
Import DDR training code from commit 1b69ce2fc0 ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
147 lines
3.6 KiB
C
147 lines
3.6 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <i2c.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
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#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
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#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
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#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
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#define REG_READ_DATA_READY_DELAYS_MASK 0x1f
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#define REG_READ_DATA_READY_DELAYS_OFFS 8
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int ddr3_if_ecc_enabled(void)
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{
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struct hws_topology_map *tm = ddr3_get_topology_map();
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if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
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DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
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return 1;
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else
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return 0;
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}
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int ddr3_pre_algo_config(void)
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{
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struct hws_topology_map *tm = ddr3_get_topology_map();
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/* Set Bus3 ECC training mode */
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if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) {
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/* Set Bus3 ECC MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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REG_SDRAM_PINS_MUX, 0x100, 0x100));
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}
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/* Set regular ECC training mode (bus4 and bus 3) */
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if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
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(DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
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/* Enable ECC Write MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x100, 0x100));
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/* General ECC enable */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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REG_SDRAM_CONFIG_ADDR, 0x40000, 0x40000));
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/* Disable Read Data ECC MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x0, 0x2));
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}
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return MV_OK;
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}
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int ddr3_post_algo_config(void)
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{
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struct hws_topology_map *tm = ddr3_get_topology_map();
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int status;
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status = ddr3_post_run_alg();
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if (MV_OK != status) {
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printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
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return status;
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}
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/* Un_set ECC training mode */
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if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
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(DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
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/* Disable ECC Write MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x0, 0x100));
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/* General ECC and Bus3 ECC MUX remains enabled */
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}
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return MV_OK;
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}
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int ddr3_hws_hw_training(void)
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{
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enum hws_algo_type algo_mode = ALGO_TYPE_DYNAMIC;
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int status;
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struct init_cntr_param init_param;
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status = ddr3_silicon_pre_init();
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if (MV_OK != status) {
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printf("DDR3 Pre silicon Config - FAILED 0x%x\n", status);
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return status;
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}
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init_param.do_mrs_phy = 1;
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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init_param.is_ctrl64_bit = 0;
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#else
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init_param.is_ctrl64_bit = 1;
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#endif
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#if defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_38X) || \
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defined(CONFIG_ARMADA_39X)
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init_param.init_phy = 1;
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#else
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init_param.init_phy = 0;
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#endif
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init_param.msys_init = 1;
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status = hws_ddr3_tip_init_controller(0, &init_param);
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if (MV_OK != status) {
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printf("DDR3 init controller - FAILED 0x%x\n", status);
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return status;
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}
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status = ddr3_silicon_post_init();
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if (MV_OK != status) {
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printf("DDR3 Post Init - FAILED 0x%x\n", status);
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return status;
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}
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status = ddr3_pre_algo_config();
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if (MV_OK != status) {
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printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
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return status;
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}
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/* run algorithm in order to configure the PHY */
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status = hws_ddr3_tip_run_alg(0, algo_mode);
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if (MV_OK != status) {
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printf("DDR3 run algorithm - FAILED 0x%x\n", status);
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return status;
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}
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status = ddr3_post_algo_config();
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if (MV_OK != status) {
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printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
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return status;
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}
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return MV_OK;
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}
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