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68abd1c308
Rename directory board/renesas/rcar-common to board/renesas/common and move files. This allows the build system to use HAVE_VENDOR_COMMON_LIB which automatically includes board/$(VENDOR)/common/Makefile . Create temporarily empty board/renesas/common/Makefile to be extended with actual content later in this series. This is a preparatory patch for board Makefile simplification. No functional change so far. Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
90 lines
1.7 KiB
C
90 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/common/gen4-common.c
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*
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* Copyright (C) 2021-2024 Renesas Electronics Corp.
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*/
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#include <asm/arch/renesas.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <linux/errno.h>
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#define RST_BASE 0xE6160000 /* Domain0 */
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#define RST_WDTRSTCR (RST_BASE + 0x10)
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#define RST_RWDT 0xA55A8002
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DECLARE_GLOBAL_DATA_PTR;
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static void init_generic_timer(void)
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{
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const u32 freq = CONFIG_SYS_CLK_FREQ;
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/* Update memory mapped and register based freqency */
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asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
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writel(freq, CNTFID0);
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/* Enable counter */
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setbits_le32(CNTCR_BASE, CNTCR_EN);
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}
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static void init_gic_v3(void)
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{
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/* GIC v3 power on */
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writel(BIT(1), GICR_LPI_PWRR);
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/* Wait till the WAKER_CA_BIT changes to 0 */
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clrbits_le32(GICR_LPI_WAKER, BIT(1));
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while (readl(GICR_LPI_WAKER) & BIT(2))
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;
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writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
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}
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void s_init(void)
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{
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if (current_el() == 3)
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init_generic_timer();
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}
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int board_early_init_f(void)
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{
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/* Unlock CPG access */
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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return 0;
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}
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int board_init(void)
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{
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if (current_el() != 3)
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return 0;
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init_gic_v3();
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/* Enable RWDT reset on V3U in EL3 */
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if (IS_ENABLED(CONFIG_R8A779A0) &&
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renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779A0) {
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writel(RST_RWDT, RST_WDTRSTCR);
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}
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return 0;
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}
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#define RST_BASE 0xE6160000 /* Domain0 */
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#define RST_SRESCR0 (RST_BASE + 0x18)
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#define RST_SPRES 0x5AA58000
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void __weak reset_cpu(void)
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{
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writel(RST_SPRES, RST_SRESCR0);
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return 0;
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}
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