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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
145 lines
3.1 KiB
C
145 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Converted to driver model by Nathan Barrett-Morrison
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*
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* Author: Greg Malysa <greg.malysa@timesys.com>
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* Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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*
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* dm timer implementation for ADI ADSP-SC5xx SoCs
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*
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*/
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/compiler_types.h>
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/*
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* Timer Configuration Register Bits
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*/
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#define TIMER_OUT_DIS 0x0800
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#define TIMER_PULSE_HI 0x0080
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#define TIMER_MODE_PWM_CONT 0x000c
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#define __BFP(m) u16 m; u16 __pad_##m
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struct gptimer3 {
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__BFP(config);
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u32 counter;
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u32 period;
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u32 width;
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u32 delay;
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};
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struct gptimer3_group_regs {
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__BFP(run);
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__BFP(enable);
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__BFP(disable);
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__BFP(stop_cfg);
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__BFP(stop_cfg_set);
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__BFP(stop_cfg_clr);
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__BFP(data_imsk);
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__BFP(stat_imsk);
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__BFP(tr_msk);
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__BFP(tr_ie);
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__BFP(data_ilat);
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__BFP(stat_ilat);
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__BFP(err_status);
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__BFP(bcast_per);
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__BFP(bcast_wid);
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__BFP(bcast_dly);
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};
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#define MAX_TIM_LOAD 0xFFFFFFFF
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struct adi_gptimer_priv {
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struct gptimer3_group_regs __iomem *timer_group;
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struct gptimer3 __iomem *timer_base;
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u32 prev;
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u64 upper;
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};
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static u64 adi_gptimer_get_count(struct udevice *udev)
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{
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struct adi_gptimer_priv *priv = dev_get_priv(udev);
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u32 now = readl(&priv->timer_base->counter);
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if (now < priv->prev)
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priv->upper += (1ull << 32);
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priv->prev = now;
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return (priv->upper + (u64)now);
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}
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static const struct timer_ops adi_gptimer_ops = {
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.get_count = adi_gptimer_get_count,
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};
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static int adi_gptimer_probe(struct udevice *udev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(udev);
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struct adi_gptimer_priv *priv = dev_get_priv(udev);
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struct clk clk;
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u16 imask;
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int ret;
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priv->timer_group = dev_remap_addr_index(udev, 0);
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priv->timer_base = dev_remap_addr_index(udev, 1);
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priv->upper = 0;
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priv->prev = 0;
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if (!priv->timer_group || !priv->timer_base) {
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dev_err(udev, "Missing timer_group or timer_base reg entries\n");
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return -ENODEV;
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}
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ret = clk_get_by_index(udev, 0, &clk);
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if (ret < 0) {
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dev_err(udev, "Missing clock reference for timer\n");
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return ret;
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}
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(udev, "Failed to enable clock\n");
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return ret;
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}
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uc_priv->clock_rate = clk_get_rate(&clk);
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/* Enable timer */
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writew(TIMER_OUT_DIS | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI,
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&priv->timer_base->config);
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writel(MAX_TIM_LOAD, &priv->timer_base->period);
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writel(MAX_TIM_LOAD - 1, &priv->timer_base->width);
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/* We only use timer 0 in uboot */
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imask = readw(&priv->timer_group->data_imsk);
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imask &= ~(1 << 0);
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writew(imask, &priv->timer_group->data_imsk);
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writew((1 << 0), &priv->timer_group->enable);
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return 0;
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}
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static const struct udevice_id adi_gptimer_ids[] = {
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{ .compatible = "adi,sc5xx-gptimer" },
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{ },
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};
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U_BOOT_DRIVER(adi_gptimer) = {
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.name = "adi_gptimer",
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.id = UCLASS_TIMER,
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.of_match = adi_gptimer_ids,
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.priv_auto = sizeof(struct adi_gptimer_priv),
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.probe = adi_gptimer_probe,
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.ops = &adi_gptimer_ops,
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};
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