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c60bdd2740
In order to use the driver model and clock system to enable UART clocks from the serial driver, it's necessary to register the UART clocks. With the helper function to check for imx6qp vs other variants, the UART can register for both scenarios. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
179 lines
6.1 KiB
C
179 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include "clk.h"
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static int imx6q_clk_request(struct clk *clk)
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{
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if (clk->id < IMX6QDL_CLK_DUMMY || clk->id >= IMX6QDL_CLK_END) {
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printf("%s: Invalid clk ID #%lu\n", __func__, clk->id);
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return -EINVAL;
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}
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return 0;
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}
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static struct clk_ops imx6q_clk_ops = {
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.request = imx6q_clk_request,
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.set_rate = ccf_clk_set_rate,
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.get_rate = ccf_clk_get_rate,
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.enable = ccf_clk_enable,
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.disable = ccf_clk_disable,
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};
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static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
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"pll2_pfd0_352m", "pll2_198m", };
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static const char *const uart_sels[] = { "pll3_80m", "osc", };
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static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
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static int imx6q_clk_probe(struct udevice *dev)
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{
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void *base;
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/* Anatop clocks */
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base = (void *)ANATOP_BASE_ADDR;
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clk_dm(IMX6QDL_CLK_PLL2,
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imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
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base + 0x30, 0x1));
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clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
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imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
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base + 0x10, 0x3));
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clk_dm(IMX6QDL_CLK_PLL3_60M,
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imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
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clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
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imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
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clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
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imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
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clk_dm(IMX6QDL_CLK_PLL6,
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imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
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clk_dm(IMX6QDL_CLK_PLL6_ENET,
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imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
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/* CCM clocks */
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base = dev_read_addr_ptr(dev);
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if (!base)
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return -EINVAL;
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clk_dm(IMX6QDL_CLK_USDHC1_SEL,
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imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
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usdhc_sels, ARRAY_SIZE(usdhc_sels)));
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clk_dm(IMX6QDL_CLK_USDHC2_SEL,
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imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
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usdhc_sels, ARRAY_SIZE(usdhc_sels)));
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clk_dm(IMX6QDL_CLK_USDHC3_SEL,
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imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
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usdhc_sels, ARRAY_SIZE(usdhc_sels)));
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clk_dm(IMX6QDL_CLK_USDHC4_SEL,
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imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
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usdhc_sels, ARRAY_SIZE(usdhc_sels)));
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if (of_machine_is_compatible("fsl,imx6qp")) {
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clk_dm(IMX6QDL_CLK_UART_SEL,
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imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels,
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ARRAY_SIZE(uart_sels)));
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clk_dm(IMX6QDL_CLK_ECSPI_SEL,
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imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels,
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ARRAY_SIZE(ecspi_sels)));
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}
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clk_dm(IMX6QDL_CLK_USDHC1_PODF,
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imx_clk_divider("usdhc1_podf", "usdhc1_sel",
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base + 0x24, 11, 3));
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clk_dm(IMX6QDL_CLK_USDHC2_PODF,
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imx_clk_divider("usdhc2_podf", "usdhc2_sel",
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base + 0x24, 16, 3));
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clk_dm(IMX6QDL_CLK_USDHC3_PODF,
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imx_clk_divider("usdhc3_podf", "usdhc3_sel",
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base + 0x24, 19, 3));
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clk_dm(IMX6QDL_CLK_USDHC4_PODF,
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imx_clk_divider("usdhc4_podf", "usdhc4_sel",
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base + 0x24, 22, 3));
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if (of_machine_is_compatible("fsl,imx6qp")) {
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clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
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imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6));
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clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
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imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
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} else {
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clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
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imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6));
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clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
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imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
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}
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clk_dm(IMX6QDL_CLK_ECSPI1,
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imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
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clk_dm(IMX6QDL_CLK_ECSPI2,
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imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
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clk_dm(IMX6QDL_CLK_ECSPI3,
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imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
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clk_dm(IMX6QDL_CLK_ECSPI4,
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imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
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clk_dm(IMX6QDL_CLK_UART_IPG,
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imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24));
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clk_dm(IMX6QDL_CLK_UART_SERIAL,
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imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26));
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clk_dm(IMX6QDL_CLK_USDHC1,
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imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
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clk_dm(IMX6QDL_CLK_USDHC2,
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imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
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clk_dm(IMX6QDL_CLK_USDHC3,
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imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
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clk_dm(IMX6QDL_CLK_USDHC4,
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imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
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clk_dm(IMX6QDL_CLK_PERIPH_PRE,
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imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
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ARRAY_SIZE(periph_pre_sels)));
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clk_dm(IMX6QDL_CLK_PERIPH,
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imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48,
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5, periph_sels, ARRAY_SIZE(periph_sels)));
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clk_dm(IMX6QDL_CLK_AHB,
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imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
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base + 0x48, 1));
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clk_dm(IMX6QDL_CLK_IPG,
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imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
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clk_dm(IMX6QDL_CLK_IPG_PER,
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imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
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clk_dm(IMX6QDL_CLK_I2C1,
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imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
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clk_dm(IMX6QDL_CLK_I2C2,
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imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
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clk_dm(IMX6QDL_CLK_I2C3,
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imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10));
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clk_dm(IMX6QDL_CLK_PWM1,
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imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16));
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clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
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clk_dm(IMX6QDL_CLK_ENET_REF,
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imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
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return 0;
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}
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static const struct udevice_id imx6q_clk_ids[] = {
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{ .compatible = "fsl,imx6q-ccm" },
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{ },
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};
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U_BOOT_DRIVER(imx6q_clk) = {
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.name = "clk_imx6q",
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.id = UCLASS_CLK,
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.of_match = imx6q_clk_ids,
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.ops = &imx6q_clk_ops,
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.probe = imx6q_clk_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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