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https://github.com/u-boot/u-boot.git
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9bc0c7e8ab
Move differences in DT files between upstream Linux DT and U-Boot DT to mt7629-rfb-u-boot.dtsi. Remove old copies of mt7629-related clock bindings, .dts, and .dtsi files. Update defconfig to switch the whole mt7629 SoC to use OF_UPSTREAM. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
159 lines
3 KiB
Text
159 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <dt-bindings/reset/mt7629-reset.h>
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/ {
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dramc: dramc@10203000 {
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compatible = "mediatek,mt7629-dramc";
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reg = <0x10203000 0x600>, /* EMI */
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<0x10213000 0x1000>, /* DDRPHY */
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<0x10214000 0xd00>; /* DRAMC_AO */
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clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
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<&topckgen CLK_TOP_SYSPLL1_D8>,
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<&topckgen CLK_TOP_MEM_SEL>,
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<&topckgen CLK_TOP_DMPLL>;
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clock-names = "phy", "phy_mux", "mem", "mem_mux";
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};
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mcucfg: syscon@10200000 {
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compatible = "mediatek,mt7629-mcucfg", "syscon";
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reg = <0x10200000 0x1000>;
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#clock-cells = <1>;
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};
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timer0: timer@10004000 {
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compatible = "mediatek,timer";
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reg = <0x10004000 0x80>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
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<&topckgen CLK_TOP_10M_SEL>;
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clock-names = "mux", "src";
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};
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snand: snand@1100d000 {
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compatible = "mediatek,mt7629-snand";
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reg = <0x1100d000 0x1000>,
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<0x1100e000 0x1000>;
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reg-names = "nfi", "ecc";
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clocks = <&pericfg CLK_PERI_NFI_PD>,
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<&pericfg CLK_PERI_SNFI_PD>,
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<&pericfg CLK_PERI_NFIECC_PD>;
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clock-names = "nfi_clk", "pad_clk", "ecc_clk";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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<&topckgen CLK_TOP_NFI_INFRA_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
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<&topckgen CLK_TOP_UNIVPLL2_D8>;
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status = "disabled";
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&watchdog>;
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};
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};
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&infracfg {
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bootph-all;
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};
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&pericfg {
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bootph-all;
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};
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&timer0 {
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bootph-all;
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};
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&mcucfg {
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bootph-all;
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};
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&dramc {
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bootph-all;
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};
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&apmixedsys {
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bootph-all;
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};
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&topckgen {
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bootph-all;
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};
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&uart0 {
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bootph-all;
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reg-shift = <2>;
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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};
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&qspi {
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bootph-all;
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_pins>;
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status = "okay";
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/delete-node/ flash@0;
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spi-flash@0{
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bootph-all;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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&pio {
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bootph-all;
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snfi_pins: snfi-pins {
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mux {
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bootph-all;
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function = "flash";
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groups = "snfi";
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};
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};
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snor_pins: snor-pins {
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mux {
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bootph-all;
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function = "flash";
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groups = "spi_nor";
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};
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};
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};
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&snand {
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pinctrl-names = "default";
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pinctrl-0 = <&snfi_pins>;
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status = "okay";
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quad-spi;
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bootph-all;
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};
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ð {
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resets = <ðsys ETHSYS_FE_RST>;
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reset-names = "fe";
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "2500base-x";
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mediatek,switch = "mt7531";
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reset-gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
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assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
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<&topckgen CLK_TOP_F10M_REF_SEL>,
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<&topckgen CLK_TOP_SGMII_REF_1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
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<&topckgen CLK_TOP_SYSPLL4_D16>,
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<&topckgen CLK_TOP_SGMIIPLL_D2>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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