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c0e1775a86
Add sysinfo platform driver for all armv8 platforms to retrieve hardware information on processor and cache. Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
292 lines
7.2 KiB
C
292 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024 Linaro Limited
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* Author: Raymond Mao <raymond.mao@linaro.org>
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*/
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#include <dm.h>
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#include <smbios_plat.h>
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#include <stdio.h>
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#include <sysinfo.h>
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union ccsidr_el1 {
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struct {
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u64 linesize:3;
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u64 associativity:10;
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u64 numsets:15;
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u64 unknown:4;
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u64 reserved:32;
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} no_ccidx;
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struct {
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u64 linesize:3;
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u64 associativity:21;
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u64 reserved1:8;
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u64 numsets:24;
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u64 reserved2:8;
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} ccidx_aarch64;
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struct {
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u64 linesize:3;
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u64 associativity:21;
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u64 reserved:8;
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u64 unallocated:32;
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} ccidx_aarch32;
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u64 data;
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};
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union midr_el1 {
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struct {
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u64 revision:4;
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u64 partnum:12;
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u64 architecture:4;
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u64 variant:4;
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u64 implementer:8;
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u64 reserved:32;
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} fields;
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u64 data;
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};
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enum {
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CACHE_NONE,
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CACHE_INST_ONLY,
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CACHE_DATA_ONLY,
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CACHE_INST_WITH_DATA,
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CACHE_UNIFIED,
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};
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enum {
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CACHE_ASSOC_DIRECT_MAPPED = 1,
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CACHE_ASSOC_2WAY = 2,
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CACHE_ASSOC_4WAY = 4,
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CACHE_ASSOC_8WAY = 8,
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CACHE_ASSOC_16WAY = 16,
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CACHE_ASSOC_12WAY = 12,
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CACHE_ASSOC_24WAY = 24,
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CACHE_ASSOC_32WAY = 32,
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CACHE_ASSOC_48WAY = 48,
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CACHE_ASSOC_64WAY = 64,
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CACHE_ASSOC_20WAY = 20,
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};
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enum {
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VENDOR_RESERVED = 0,
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VENDOR_ARM = 0x41,
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VENDOR_BROADCOM = 0x42,
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VENDOR_CAVIUM = 0x43,
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VENDOR_DEC = 0x44,
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VENDOR_FUJITSU = 0x46,
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VENDOR_INFINEON = 0x49,
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VENDOR_FREESCALE = 0x4d,
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VENDOR_NVIDIA = 0x4e,
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VENDOR_AMCC = 0x50,
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VENDOR_QUALCOMM = 0x51,
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VENDOR_MARVELL = 0x56,
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VENDOR_INTEL = 0x69,
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VENDOR_AMPERE = 0xc0,
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};
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/*
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* TODO:
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* To support ARMv8.3, we need to read "CCIDX, bits [23:20]" from
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* ID_AA64MMFR2_EL1 to get the format of CCSIDR_EL1:
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*
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* 0b0000 - 32-bit format implemented for all levels of the CCSIDR_EL1.
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* 0b0001 - 64-bit format implemented for all levels of the CCSIDR_EL1.
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*
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* Here we assume to use CCSIDR_EL1 in no CCIDX layout:
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* NumSets, bits [27:13]: (Number of sets in cache) - 1
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* Associativity, bits [12:3]: (Associativity of cache) - 1
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* LineSize, bits [2:0]: (Log2(Number of bytes in cache line)) - 4
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*/
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int sysinfo_get_cache_info(u8 level, struct cache_info *cinfo)
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{
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u64 clidr_el1;
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u32 csselr_el1;
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u32 num_sets;
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union ccsidr_el1 creg;
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int cache_type;
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sysinfo_cache_info_default(cinfo);
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/* Read CLIDR_EL1 */
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asm volatile("mrs %0, clidr_el1" : "=r" (clidr_el1));
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debug("CLIDR_EL1: 0x%llx\n", clidr_el1);
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cache_type = (clidr_el1 >> (3 * level)) & 0x7;
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if (cache_type == CACHE_NONE) /* level does not exist */
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return -1;
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switch (cache_type) {
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case CACHE_INST_ONLY:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_INST;
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break;
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case CACHE_DATA_ONLY:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_DATA;
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break;
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case CACHE_UNIFIED:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNIFIED;
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break;
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case CACHE_INST_WITH_DATA:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_OTHER;
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break;
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default:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN;
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break;
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}
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/* Select cache level */
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csselr_el1 = (level << 1);
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asm volatile("msr csselr_el1, %0" : : "r" (csselr_el1));
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/* Read CCSIDR_EL1 */
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asm volatile("mrs %0, ccsidr_el1" : "=r" (creg.data));
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debug("CCSIDR_EL1 (Level %d): 0x%llx\n", level + 1, creg.data);
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/* Extract cache size and associativity */
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cinfo->line_size = 1 << (creg.no_ccidx.linesize + 4);
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/* Map the associativity value */
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switch (creg.no_ccidx.associativity + 1) {
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case CACHE_ASSOC_DIRECT_MAPPED:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_DMAPPED;
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break;
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case CACHE_ASSOC_2WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_2WAY;
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break;
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case CACHE_ASSOC_4WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_4WAY;
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break;
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case CACHE_ASSOC_8WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_8WAY;
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break;
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case CACHE_ASSOC_16WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_16WAY;
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break;
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case CACHE_ASSOC_12WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_12WAY;
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break;
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case CACHE_ASSOC_24WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_24WAY;
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break;
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case CACHE_ASSOC_32WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_32WAY;
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break;
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case CACHE_ASSOC_48WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_48WAY;
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break;
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case CACHE_ASSOC_64WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_64WAY;
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break;
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case CACHE_ASSOC_20WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_20WAY;
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break;
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default:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_UNKNOWN;
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break;
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}
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num_sets = creg.no_ccidx.numsets + 1;
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/* Size in KB */
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cinfo->max_size = (cinfo->associativity * num_sets * cinfo->line_size) /
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1024;
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debug("L%d Cache:\n", level + 1);
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debug("Number of bytes in cache line:%u\n", cinfo->line_size);
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debug("Associativity of cache:%u\n", cinfo->associativity);
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debug("Number of sets in cache:%u\n", num_sets);
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debug("Cache size in KB:%u\n", cinfo->max_size);
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cinfo->inst_size = cinfo->max_size;
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/*
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* Below fields with common values are placed under DT smbios node
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* socket-design, config
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* Other fields are typically specific to the implementation of the ARM
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* processor by the silicon vendor:
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* supp_sram_type, curr_sram_type, speed, err_corr_type
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*/
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return 0;
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}
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int sysinfo_get_processor_info(struct processor_info *pinfo)
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{
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u64 mpidr, core_count;
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union midr_el1 midr;
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/* Read the MIDR_EL1 register */
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asm volatile("mrs %0, MIDR_EL1" : "=r"(midr.data));
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/* Read the MPIDR_EL1 register */
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asm volatile("mrs %0, MPIDR_EL1" : "=r"(mpidr));
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debug("MIDR: 0x%016llx\n", midr.data);
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debug("MPIDR: 0x%016llx\n", mpidr);
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debug("CPU Implementer: 0x%02x\n", midr.fields.implementer);
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switch (midr.fields.implementer) {
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case VENDOR_ARM:
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pinfo->manufacturer = "ARM Limited";
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break;
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case VENDOR_BROADCOM:
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pinfo->manufacturer = "Broadcom Corporation";
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break;
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case VENDOR_CAVIUM:
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pinfo->manufacturer = "Cavium Inc";
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break;
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case VENDOR_DEC:
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pinfo->manufacturer = "Digital Equipment Corporation";
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break;
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case VENDOR_FUJITSU:
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pinfo->manufacturer = "Fujitsu Ltd";
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break;
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case VENDOR_INFINEON:
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pinfo->manufacturer = "Infineon Technologies AG";
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break;
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case VENDOR_FREESCALE:
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pinfo->manufacturer = "Freescale Semiconductor Inc";
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break;
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case VENDOR_NVIDIA:
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pinfo->manufacturer = "NVIDIA Corporation";
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break;
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case VENDOR_AMCC:
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pinfo->manufacturer =
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"Applied Micro Circuits Corporation";
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break;
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case VENDOR_QUALCOMM:
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pinfo->manufacturer = "Qualcomm Inc";
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break;
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case VENDOR_MARVELL:
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pinfo->manufacturer = "Marvell International Ltd";
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break;
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case VENDOR_INTEL:
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pinfo->manufacturer = "Intel Corporation";
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break;
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case VENDOR_AMPERE:
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pinfo->manufacturer = "Ampere Computing";
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break;
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default:
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pinfo->manufacturer = "Unknown";
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break;
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}
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debug("CPU part number: 0x%x\n", midr.fields.partnum);
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debug("CPU revision: 0x%x\n", midr.fields.revision);
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debug("CPU architecture: 0x%x\n", midr.fields.architecture);
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debug("CPU variant: 0x%x\n", midr.fields.variant);
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/* Extract number of cores */
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core_count = (mpidr >> 0) & 0xFF;
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pinfo->core_count = core_count + 1;
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debug("CPU Core Count: %d\n", pinfo->core_count);
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pinfo->core_enabled = pinfo->core_count;
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pinfo->characteristics = SMBIOS_PROCESSOR_64BIT |
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SMBIOS_PROCESSOR_ARM64_SOCID;
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if (pinfo->core_count > 1)
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pinfo->characteristics |= SMBIOS_PROCESSOR_MULTICORE;
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/*
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* Below fields with common values are placed under DT smbios node
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* version, processor-type, processor-status, upgrade, family2,
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* socket-design, serial, asset-tag, part-number
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*/
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return 0;
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}
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