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0c9c501a87
Add Support for the Host Controller driver for UFS HC present on Qualcomm Snapdragon SoCs. It has been successfully tested on SDM845, SM8250, SM8550 ant SM8650 SoCs. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Tested-by: Julius Lehmann <lehmanju@devpi.de> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> #rb3gen2 Link: https://lore.kernel.org/r/20240910-topic-ufs-qcom-controller-v1-4-54c0d2231b10@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
147 lines
4.2 KiB
C
147 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef UFS_QCOM_H_
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#define UFS_QCOM_H_
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#include <reset.h>
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#include <linux/bitfield.h>
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#define MPHY_TX_FSM_STATE 0x41
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#define TX_FSM_HIBERN8 0x1
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#define DEFAULT_CLK_RATE_HZ 1000000
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#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28)
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#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16)
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#define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
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/* QCOM UFS host controller vendor specific registers */
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enum {
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REG_UFS_SYS1CLK_1US = 0xC0,
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REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
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REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
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REG_UFS_PA_ERR_CODE = 0xCC,
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/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
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REG_UFS_PARAM0 = 0xD0,
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/* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
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REG_UFS_CFG0 = 0xD8,
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REG_UFS_CFG1 = 0xDC,
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REG_UFS_CFG2 = 0xE0,
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REG_UFS_HW_VERSION = 0xE4,
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UFS_TEST_BUS = 0xE8,
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UFS_TEST_BUS_CTRL_0 = 0xEC,
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UFS_TEST_BUS_CTRL_1 = 0xF0,
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UFS_TEST_BUS_CTRL_2 = 0xF4,
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UFS_UNIPRO_CFG = 0xF8,
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/*
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* QCOM UFS host controller vendor specific registers
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* added in HW Version 3.0.0
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*/
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UFS_AH8_CFG = 0xFC,
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REG_UFS_CFG3 = 0x271C,
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};
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/* bit definitions for REG_UFS_CFG0 register */
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#define QUNIPRO_G4_SEL BIT(5)
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/* bit definitions for REG_UFS_CFG1 register */
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#define QUNIPRO_SEL BIT(0)
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#define UFS_PHY_SOFT_RESET BIT(1)
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#define UTP_DBG_RAMS_EN BIT(17)
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#define TEST_BUS_EN BIT(18)
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#define TEST_BUS_SEL GENMASK(22, 19)
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#define UFS_REG_TEST_BUS_EN BIT(30)
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#define UFS_PHY_RESET_ENABLE 1
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#define UFS_PHY_RESET_DISABLE 0
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/* bit definitions for REG_UFS_CFG2 register */
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#define UAWM_HW_CGC_EN BIT(0)
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#define UARM_HW_CGC_EN BIT(1)
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#define TXUC_HW_CGC_EN BIT(2)
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#define RXUC_HW_CGC_EN BIT(3)
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#define DFC_HW_CGC_EN BIT(4)
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#define TRLUT_HW_CGC_EN BIT(5)
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#define TMRLUT_HW_CGC_EN BIT(6)
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#define OCSC_HW_CGC_EN BIT(7)
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/* bit definitions for REG_UFS_PARAM0 */
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#define MAX_HS_GEAR_MASK GENMASK(6, 4)
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#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x))
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/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
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#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
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#define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
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TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
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DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
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TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
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/* bit offset */
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#define OFFSET_CLK_NS_REG 0xa
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/* bit masks */
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#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0)
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#define MASK_CLK_NS_REG GENMASK(23, 10)
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/* QUniPro Vendor specific attributes */
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#define PA_VS_CONFIG_REG1 0x9000
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#define DME_VS_CORE_CLK_CTRL 0xD002
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/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
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#define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16)
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#define CLK_1US_CYCLES_MASK GENMASK(7, 0)
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#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
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#define PA_VS_CORE_CLK_40NS_CYCLES 0x9007
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#define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0)
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/* QCOM UFS host controller core clk frequencies */
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#define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38
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#define UNIPRO_CORE_CLK_FREQ_75_MHZ 75
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#define UNIPRO_CORE_CLK_FREQ_100_MHZ 100
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#define UNIPRO_CORE_CLK_FREQ_150_MHZ 150
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#define UNIPRO_CORE_CLK_FREQ_300_MHZ 300
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#define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202
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#define UNIPRO_CORE_CLK_FREQ_403_MHZ 403
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static inline void
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ufs_qcom_get_controller_revision(struct ufs_hba *hba,
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u8 *major, u16 *minor, u16 *step)
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{
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u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
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*major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
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*minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
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*step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
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};
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/* Host controller hardware version: major.minor.step */
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struct ufs_hw_version {
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u16 step;
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u16 minor;
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u8 major;
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};
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struct gpio_desc;
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struct ufs_qcom_priv {
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struct phy *generic_phy;
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struct ufs_hba *hba;
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struct clk_bulk clks;
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bool is_clks_enabled;
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struct ufs_hw_version hw_ver;
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/* Reset control of HCI */
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struct reset_ctl core_reset;
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struct gpio_desc reset;
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bool is_dev_ref_clk_enabled;
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};
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#endif /* UFS_QCOM_H_ */
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