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fe11aa0b8c
Cadence SDMMC v6 controller has a lot of changes on initialize compared to v4 controller. PHY is needed by v6 controller. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Co-developed-by: Alex Soo <yuklin.soo@starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#ifndef SDHCI_CADENCE_H_
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#define SDHCI_CADENCE_H_
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/* HRS - Host Register Set (specific to Cadence) */
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/* PHY access port */
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#define SDHCI_CDNS_HRS04 0x10
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/* Cadence V4 HRS04 Description*/
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#define SDHCI_CDNS_HRS04_ACK BIT(26)
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#define SDHCI_CDNS_HRS04_RD BIT(25)
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#define SDHCI_CDNS_HRS04_WR BIT(24)
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#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
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#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
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#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
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#define SDHCI_CDNS_HRS05 0x14
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/* eMMC control */
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#define SDHCI_CDNS_HRS06 0x18
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#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
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#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
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#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
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#define SDHCI_CDNS_HRS06_MODE_SD 0x0
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#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
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#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
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/* SRS - Slot Register Set (SDHCI-compatible) */
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#define SDHCI_CDNS_SRS_BASE 0x200
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/* Cadence V4 PHY Setting*/
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#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
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#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
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#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
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#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
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#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
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#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
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#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
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#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
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#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
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/*
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* The tuned val register is 6 bit-wide, but not the whole of the range is
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* available. The range 0-42 seems to be available (then 43 wraps around to 0)
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* but I am not quite sure if it is official. Use only 0 to 39 for safety.
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*/
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#define SDHCI_CDNS_MAX_TUNING_LOOP 40
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struct sdhci_cdns_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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void __iomem *hrs_addr;
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};
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int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode);
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int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat);
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int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val);
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#endif
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