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cae6e8993c
Import DDR training code from commit 1b69ce2fc0 ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
85 lines
3 KiB
C
85 lines
3 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_IP_ENGINE_H_
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#define _DDR3_TRAINING_IP_ENGINE_H_
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#include "ddr3_training_ip_def.h"
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#include "ddr3_training_ip_flow.h"
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#define EDGE_1 0
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#define EDGE_2 1
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#define ALL_PUP_TRAINING 0xe
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#define PUP_RESULT_EDGE_1_MASK 0xff
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#define PUP_RESULT_EDGE_2_MASK (0xff << 8)
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#define PUP_LOCK_RESULT_BIT 25
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#define GET_TAP_RESULT(reg, edge) \
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(((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \
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(((reg) & PUP_RESULT_EDGE_2_MASK) >> 8));
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#define GET_LOCK_RESULT(reg) \
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(((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT)
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#define EDGE_FAILURE 128
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#define ALL_BITS_PER_PUP 128
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#define MIN_WINDOW_SIZE 6
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#define MAX_WINDOW_SIZE_RX 32
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#define MAX_WINDOW_SIZE_TX 64
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int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
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enum hws_search_dir search_dir,
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enum hws_dir direction,
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enum hws_edge_compare edge,
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u32 init_val1, u32 init_val2,
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u32 num_of_iterations, u32 start_pattern,
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u32 end_pattern);
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int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
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int ddr3_tip_load_pattern_to_mem_by_cpu(u32 dev_num, enum hws_pattern pattern,
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u32 offset);
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int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
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int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
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enum hws_access_type pup_access_type,
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u32 pup_num, u32 bit_num,
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enum hws_search_dir search,
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enum hws_dir direction,
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enum hws_training_result result_type,
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enum hws_training_load_op operation,
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u32 cs_num_type, u32 **load_res,
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int is_read_from_db, u8 cons_tap,
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int is_check_result_validity);
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int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
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u32 interface_num,
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enum hws_access_type pup_access_type,
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u32 pup_num, enum hws_training_result result_type,
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enum hws_control_element control_element,
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enum hws_search_dir search_dir, enum hws_dir direction,
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u32 interface_mask, u32 init_value, u32 num_iter,
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enum hws_pattern pattern,
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enum hws_edge_compare edge_comp,
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enum hws_ddr_cs cs_type, u32 cs_num,
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enum hws_training_ip_stat *train_status);
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int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
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u32 if_id,
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enum hws_access_type pup_access_type,
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u32 pup_num,
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enum hws_training_result result_type,
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enum hws_control_element control_element,
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enum hws_search_dir search_dir,
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enum hws_dir direction,
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u32 interface_mask, u32 init_value1,
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u32 init_value2, u32 num_iter,
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enum hws_pattern pattern,
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enum hws_edge_compare edge_comp,
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enum hws_ddr_cs train_cs_type, u32 cs_num,
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enum hws_training_ip_stat *train_status);
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int is_odpg_access_done(u32 dev_num, u32 if_id);
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void ddr3_tip_print_bist_res(void);
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struct pattern_info *ddr3_tip_get_pattern_table(void);
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u16 *ddr3_tip_get_mask_results_dq_reg(void);
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u16 *ddr3_tip_get_mask_results_pup_reg_map(void);
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#endif /* _DDR3_TRAINING_IP_ENGINE_H_ */
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