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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
36 lines
702 B
C
36 lines
702 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <dm.h>
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#include <clk-uclass.h>
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#include <dt-bindings/clock/intel-clock.h>
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static ulong intel_clk_get_rate(struct clk *clk)
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{
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switch (clk->id) {
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case CLK_I2C:
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/* Hard-coded to 133MHz on current platforms */
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return 133333333;
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default:
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return -ENODEV;
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}
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}
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static struct clk_ops intel_clk_ops = {
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.get_rate = intel_clk_get_rate,
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};
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static const struct udevice_id intel_clk_ids[] = {
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{ .compatible = "intel,apl-clk" },
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{ }
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};
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U_BOOT_DRIVER(intel_apl_clk) = {
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.name = "intel_apl_clk",
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.id = UCLASS_CLK,
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.of_match = intel_clk_ids,
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.ops = &intel_clk_ops,
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};
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