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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
50 lines
1,018 B
C
50 lines
1,018 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
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* Copyright (C) 2013 Xilinx, Inc. All rights reserved.
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*/
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#include <clk.h>
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#include <dm.h>
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#include <init.h>
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#include <malloc.h>
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#include <asm/arch/clk.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* set_cpu_clk_info() - Setup clock information
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*
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* This function is called from common code after relocation and sets up the
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* clock information.
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*/
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int set_cpu_clk_info(void)
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{
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struct clk clk;
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struct udevice *dev;
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ulong rate;
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int i, ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(zynq_clk), &dev);
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if (ret)
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return ret;
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for (i = 0; i < 2; i++) {
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clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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return ret;
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rate = clk_get_rate(&clk) / 1000000;
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if (i) {
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gd->bd->bi_ddr_freq = rate;
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} else {
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gd->bd->bi_arm_freq = rate;
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gd->cpu_clk = clk_get_rate(&clk);
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}
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}
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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