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a810aa8da7
Move the log_debug() calls on top of the bit manipulation code. No functional change. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de>
276 lines
6.8 KiB
C
276 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024, Marek Vasut <marex@denx.de>
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*
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* This is code moved from drivers/net/dwc_eth_qos.c , which is:
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*/
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#include <common.h>
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#include <asm/cache.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <errno.h>
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#include <eth_phy.h>
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#include <log.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <wait_bit.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include "dwc_eth_qos.h"
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/* SYSCFG registers */
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#define SYSCFG_PMCSETR 0x04
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#define SYSCFG_PMCCLRR 0x44
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#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
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#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
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#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
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#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0x0
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#define SYSCFG_PMCSETR_ETH_SEL_RGMII 0x1
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#define SYSCFG_PMCSETR_ETH_SEL_RMII 0x4
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static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
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{
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struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
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if (!CONFIG_IS_ENABLED(CLK))
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return 0;
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return clk_get_rate(&eqos->clk_master_bus);
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}
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static int eqos_start_clks_stm32(struct udevice *dev)
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{
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struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
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int ret;
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if (!CONFIG_IS_ENABLED(CLK))
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return 0;
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debug("%s(dev=%p):\n", __func__, dev);
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ret = clk_enable(&eqos->clk_master_bus);
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if (ret < 0) {
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pr_err("clk_enable(clk_master_bus) failed: %d", ret);
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goto err;
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}
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ret = clk_enable(&eqos->clk_rx);
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if (ret < 0) {
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pr_err("clk_enable(clk_rx) failed: %d", ret);
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goto err_disable_clk_master_bus;
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}
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ret = clk_enable(&eqos->clk_tx);
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if (ret < 0) {
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pr_err("clk_enable(clk_tx) failed: %d", ret);
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goto err_disable_clk_rx;
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}
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if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
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ret = clk_enable(&eqos->clk_ck);
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if (ret < 0) {
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pr_err("clk_enable(clk_ck) failed: %d", ret);
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goto err_disable_clk_tx;
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}
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eqos->clk_ck_enabled = true;
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}
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debug("%s: OK\n", __func__);
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return 0;
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err_disable_clk_tx:
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clk_disable(&eqos->clk_tx);
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err_disable_clk_rx:
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clk_disable(&eqos->clk_rx);
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err_disable_clk_master_bus:
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clk_disable(&eqos->clk_master_bus);
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err:
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debug("%s: FAILED: %d\n", __func__, ret);
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return ret;
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}
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static int eqos_stop_clks_stm32(struct udevice *dev)
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{
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struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
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if (!CONFIG_IS_ENABLED(CLK))
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return 0;
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debug("%s(dev=%p):\n", __func__, dev);
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clk_disable(&eqos->clk_tx);
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clk_disable(&eqos->clk_rx);
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clk_disable(&eqos->clk_master_bus);
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debug("%s: OK\n", __func__);
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return 0;
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}
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static int eqos_probe_syscfg_stm32(struct udevice *dev,
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phy_interface_t interface_type)
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{
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bool eth_ref_clk_sel_reg = false;
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bool eth_clk_sel_reg = false;
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u8 *syscfg;
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u32 value;
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/* Gigabit Ethernet 125MHz clock selection. */
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eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
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/* Ethernet 50Mhz RMII clock selection */
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eth_ref_clk_sel_reg = dev_read_bool(dev, "st,eth-ref-clk-sel");
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syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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if (!syscfg)
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return -ENODEV;
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switch (interface_type) {
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case PHY_INTERFACE_MODE_MII:
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log_debug("PHY_INTERFACE_MODE_MII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
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value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
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break;
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case PHY_INTERFACE_MODE_GMII:
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log_debug("PHY_INTERFACE_MODE_GMII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
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if (eth_clk_sel_reg)
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value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
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break;
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case PHY_INTERFACE_MODE_RMII:
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log_debug("PHY_INTERFACE_MODE_RMII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_RMII);
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if (eth_ref_clk_sel_reg)
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value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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log_debug("PHY_INTERFACE_MODE_RGMII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_RGMII);
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if (eth_clk_sel_reg)
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value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
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break;
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default:
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log_debug("Do not manage %d interface\n",
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interface_type);
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/* Do not manage others interfaces */
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return -EINVAL;
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}
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/* clear and set ETH configuration bits */
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writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
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SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
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syscfg + SYSCFG_PMCCLRR);
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writel(value, syscfg + SYSCFG_PMCSETR);
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return 0;
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}
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static int eqos_probe_resources_stm32(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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phy_interface_t interface;
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int ret;
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debug("%s(dev=%p):\n", __func__, dev);
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interface = eqos->config->interface(dev);
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if (interface == PHY_INTERFACE_MODE_NA) {
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pr_err("Invalid PHY interface\n");
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return -EINVAL;
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}
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ret = eqos_probe_syscfg_stm32(dev, interface);
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if (ret)
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return -EINVAL;
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ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
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if (ret) {
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pr_err("clk_get_by_name(master_bus) failed: %d", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
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if (ret) {
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pr_err("clk_get_by_name(rx) failed: %d", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
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if (ret) {
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pr_err("clk_get_by_name(tx) failed: %d", ret);
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goto err_probe;
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}
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/* Get ETH_CLK clocks (optional) */
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ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
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if (ret)
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pr_warn("No phy clock provided %d", ret);
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debug("%s: OK\n", __func__);
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return 0;
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err_probe:
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debug("%s: returns %d\n", __func__, ret);
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return ret;
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}
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static int eqos_remove_resources_stm32(struct udevice *dev)
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{
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debug("%s(dev=%p):\n", __func__, dev);
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return 0;
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}
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static struct eqos_ops eqos_stm32_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_stm32,
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.eqos_remove_resources = eqos_remove_resources_stm32,
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.eqos_stop_resets = eqos_null_ops,
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.eqos_start_resets = eqos_null_ops,
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.eqos_stop_clks = eqos_stop_clks_stm32,
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.eqos_start_clks = eqos_start_clks_stm32,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_null_ops,
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.eqos_get_enetaddr = eqos_null_ops,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
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};
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struct eqos_config __maybe_unused eqos_stm32mp15_config = {
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.reg_access_always_ok = false,
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.mdio_wait = 10000,
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.swr_wait = 50,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
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.axi_bus_width = EQOS_AXI_WIDTH_64,
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.interface = dev_read_phy_mode,
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.ops = &eqos_stm32_ops
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};
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