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994a51d9ac
Add support for the Polyhex Debix Model A SBC board. It is an industrial grade single board computer based on NXP's i.MX 8M Plus. Currently supported interfaces are: - Serial console - Micro SD - eQOS and FEC Ethernet imx8mp-debix-model-a.dts is taken from Linux 6.3. Signed-off-by: Gilles Talis <gilles.talis@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
129 lines
2.6 KiB
C
129 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2018-2019, 2021 NXP
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* Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/sections.h>
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#include <common.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <power/pca9450.h>
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#include <power/pmic.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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/*
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* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
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* not allow to change it. Should set the clock after PMIC
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* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
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* set by ROM for ND VDD_SOC
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*/
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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puts("Normal Boot\n");
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}
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static int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@25", &dev);
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if (ret == -ENODEV) {
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puts("Failed to get PMIC\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output. */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
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if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
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/* Set DVS0 to 0.85V for special case. */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
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else
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
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/* Set DVS1 to 0.85v for suspend. */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
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/*
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* Enable DVS control through PMIC_STBY_REQ and
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* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
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*/
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/*
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* Kernel uses OD/OD frequency for SoC.
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* To avoid timing risk from SoC to ARM,
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* increase VDD_ARM to OD voltage 0.95V
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*/
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pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
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return 0;
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}
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int board_fit_config_name_match(const char *name)
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{
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if (is_imx8mp() &&
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!strcmp(name, "imx8mp-debix-model-a"))
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return 0;
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return -1;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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