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https://github.com/u-boot/u-boot.git
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a1a47d3c57
In case we are still at relocation target address before relocation we do not need to load the registers needed for relocation. We should instead skip the whole relocation part and jump over to clear_bss immediately. Signed-off-by: Andreas Biemann <andreas.devel@googlemail.com>
351 lines
7.6 KiB
ArmAsm
351 lines
7.6 KiB
ArmAsm
/*
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* Startup Code for S3C44B0 CPU-core
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*
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* (C) Copyright 2004
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* DAVE Srl
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*
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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/*
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* Jump vector table
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*/
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.globl _start
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_start: b reset
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* relocate u-boot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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/*
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* These are defined in the board-specific linker script.
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* Subtracting _start from them lets the linker put their
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* relative position in the executable instead of leaving
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* them null.
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*/
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.globl _bss_start_ofs
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_bss_start_ofs:
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.word __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.word _end - _start
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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bl lowlevel_init
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#endif
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/* Set stackpointer in internal RAM to call board_init_f */
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call_board_init_f:
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ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
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bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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ldr r0,=0x00000000
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bl board_init_f
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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.globl relocate_code
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relocate_code:
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mov r4, r0 /* save addr_sp */
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mov r5, r1 /* save addr of gd */
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mov r6, r2 /* save addr of destination */
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/* Set up the stack */
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stack_setup:
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mov sp, r4
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adr r0, _start
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cmp r0, r6
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beq clear_bss /* skip relocation */
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mov r1, r6 /* r1 <- scratch for copy_loop */
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ldr r2, _TEXT_BASE
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ldr r3, _bss_start_ofs
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add r2, r0, r3 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r9-r10} /* copy from source address [r0] */
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stmia r1!, {r9-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#ifndef CONFIG_PRELOADER
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/*
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* fix .rel.dyn relocations
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*/
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ldr r0, _TEXT_BASE /* r0 <- Text base */
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sub r9, r6, r0 /* r9 <- relocation offset */
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ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
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add r10, r10, r0 /* r10 <- sym table in FLASH */
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ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
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add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
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ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
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add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
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fixloop:
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ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
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add r0, r0, r9 /* r0 <- location to fix up in RAM */
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ldr r1, [r2, #4]
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and r8, r1, #0xff
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cmp r8, #23 /* relative fixup? */
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beq fixrel
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cmp r8, #2 /* absolute fixup? */
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beq fixabs
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/* ignore unknown type of fixup */
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b fixnext
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fixabs:
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/* absolute fix: set location to (offset) symbol value */
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mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
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add r1, r10, r1 /* r1 <- address of symbol in table */
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ldr r1, [r1, #4] /* r1 <- symbol value */
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add r1, r9 /* r1 <- relocated sym addr */
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b fixnext
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fixrel:
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/* relative fix: increase location by offset */
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ldr r1, [r0]
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add r1, r1, r9
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fixnext:
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str r1, [r0]
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add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
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cmp r2, r3
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blo fixloop
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#endif
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clear_bss:
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#ifndef CONFIG_PRELOADER
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ldr r0, _bss_start_ofs
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ldr r1, _bss_end_ofs
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ldr r3, _TEXT_BASE /* Text base */
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mov r4, r6 /* reloc addr */
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add r0, r0, r4
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add r1, r1, r4
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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bl coloured_LED_init
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bl red_LED_on
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#endif
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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ldr r0, _board_init_r_ofs
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adr r1, _start
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add lr, r0, r1
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add lr, lr, r9
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/* setup parameters for board_init_r */
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mov r0, r5 /* gd_t */
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mov r1, r6 /* dest_addr */
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/* jump to it ... */
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mov pc, lr
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_board_init_r_ofs:
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.word board_init_r - _start
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_rel_dyn_start_ofs:
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.word __rel_dyn_start - _start
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_rel_dyn_end_ofs:
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.word __rel_dyn_end - _start
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_dynsym_start_ofs:
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.word __dynsym_start - _start
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#define INTCON (0x01c00000+0x200000)
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#define INTMSK (0x01c00000+0x20000c)
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#define LOCKTIME (0x01c00000+0x18000c)
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#define PLLCON (0x01c00000+0x180000)
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#define CLKCON (0x01c00000+0x180004)
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#define WTCON (0x01c00000+0x130000)
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cpu_init_crit:
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/* disable watch dog */
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ldr r0, =WTCON
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ldr r1, =0x0
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str r1, [r0]
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/*
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* mask all IRQs by clearing all bits in the INTMRs
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*/
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ldr r1,=INTMSK
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ldr r0, =0x03fffeff
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str r0, [r1]
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ldr r1, =INTCON
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ldr r0, =0x05
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str r0, [r1]
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/* Set Clock Control Register */
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ldr r1, =LOCKTIME
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ldrb r0, =800
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strb r0, [r1]
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ldr r1, =PLLCON
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#if CONFIG_S3C44B0_CLOCK_SPEED==66
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ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
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#elif CONFIG_S3C44B0_CLOCK_SPEED==75
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ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
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#else
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# error CONFIG_S3C44B0_CLOCK_SPEED undefined
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#endif
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str r0, [r1]
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ldr r1,=CLKCON
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ldr r0, =0x7ff8
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str r0, [r1]
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mov pc, lr
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/*************************************************/
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/* interrupt vectors */
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/*************************************************/
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real_vectors:
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b reset
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b undefined_instruction
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b software_interrupt
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b prefetch_abort
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b data_abort
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b not_used
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b irq
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b fiq
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/*************************************************/
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undefined_instruction:
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mov r6, #3
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b reset
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software_interrupt:
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mov r6, #4
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b reset
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prefetch_abort:
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mov r6, #5
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b reset
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data_abort:
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mov r6, #6
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b reset
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not_used:
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/* we *should* never reach this */
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mov r6, #7
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b reset
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irq:
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mov r6, #8
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b reset
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fiq:
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mov r6, #9
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b reset
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