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Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
21 lines
470 B
Text
21 lines
470 B
Text
menu "i.MX9 DDR controllers"
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depends on ARCH_IMX9
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config IMX9_DRAM
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bool "imx9 dram"
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select IMX_SNPS_DDR_PHY
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config IMX9_LPDDR4X
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bool "imx9 lpddr4 and lpddr4x"
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select IMX9_DRAM
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help
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Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
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config SAVED_DRAM_TIMING_BASE
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hex "Define the base address for saved dram timing"
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help
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after DRAM is trained, need to save the dram related timming
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info into memory for low power use.
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default 0x204DC000
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endmenu
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