mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-29 17:55:48 +00:00
93b4abd3a2
Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
|
|
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/pl310.h>
|
|
#include <asm/u-boot.h>
|
|
#include <asm/utils.h>
|
|
#include <image.h>
|
|
#include <asm/arch/reset_manager.h>
|
|
#include <spl.h>
|
|
#include <asm/arch/system_manager.h>
|
|
#include <asm/arch/freeze_controller.h>
|
|
#include <asm/arch/clock_manager.h>
|
|
#include <asm/arch/scan_manager.h>
|
|
#include <asm/arch/sdram.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
static struct pl310_regs *const pl310 =
|
|
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
struct socfpga_system_manager *sysmgr_regs =
|
|
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
|
|
unsigned long reg;
|
|
/*
|
|
* First C code to run. Clear fake OCRAM ECC first as SBE
|
|
* and DBE might triggered during power on
|
|
*/
|
|
reg = readl(&sysmgr_regs->eccgrp_ocram);
|
|
if (reg & SYSMGR_ECC_OCRAM_SERR)
|
|
writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
|
|
&sysmgr_regs->eccgrp_ocram);
|
|
if (reg & SYSMGR_ECC_OCRAM_DERR)
|
|
writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
|
|
&sysmgr_regs->eccgrp_ocram);
|
|
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* Remap SDRAM to 0x0 */
|
|
writel(0x1, &pl310->pl310_addr_filter_start);
|
|
|
|
board_init_r(NULL, 0);
|
|
}
|
|
|
|
u32 spl_boot_device(void)
|
|
{
|
|
return BOOT_DEVICE_RAM;
|
|
}
|
|
|
|
/*
|
|
* Board initialization after bss clearance
|
|
*/
|
|
void spl_board_init(void)
|
|
{
|
|
unsigned long sdram_size;
|
|
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
|
|
const struct cm_config *cm_default_cfg = cm_get_default_config();
|
|
#endif
|
|
|
|
debug("Freezing all I/O banks\n");
|
|
/* freeze all IO banks */
|
|
sys_mgr_frzctrl_freeze_req();
|
|
|
|
socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
|
|
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
|
|
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
|
|
|
|
timer_init();
|
|
|
|
debug("Reconfigure Clock Manager\n");
|
|
/* reconfigure the PLLs */
|
|
cm_basic_init(cm_default_cfg);
|
|
|
|
/* Enable bootrom to configure IOs. */
|
|
sysmgr_enable_warmrstcfgio();
|
|
|
|
/* configure the IOCSR / IO buffer settings */
|
|
if (scan_mgr_configure_iocsr())
|
|
hang();
|
|
|
|
/* configure the pin muxing through system manager */
|
|
sysmgr_pinmux_init();
|
|
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
|
|
|
|
/* de-assert reset for peripherals and bridges based on handoff */
|
|
reset_deassert_peripherals_handoff();
|
|
|
|
debug("Unfreezing/Thaw all I/O banks\n");
|
|
/* unfreeze / thaw all IO banks */
|
|
sys_mgr_frzctrl_thaw_req();
|
|
|
|
/* enable console uart printing */
|
|
preloader_console_init();
|
|
|
|
if (sdram_mmr_init_full(0xffffffff) != 0) {
|
|
puts("SDRAM init failed.\n");
|
|
hang();
|
|
}
|
|
|
|
debug("SDRAM: Calibrating PHY\n");
|
|
/* SDRAM calibration */
|
|
if (sdram_calibration_full() == 0) {
|
|
puts("SDRAM calibration failed.\n");
|
|
hang();
|
|
}
|
|
|
|
sdram_size = sdram_calculate_size();
|
|
debug("SDRAM: %ld MiB\n", sdram_size >> 20);
|
|
|
|
/* Sanity check ensure correct SDRAM size specified */
|
|
if (get_ram_size(0, sdram_size) != sdram_size) {
|
|
puts("SDRAM size check failed!\n");
|
|
hang();
|
|
}
|
|
}
|