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cae6e8993c
Import DDR training code from commit 1b69ce2fc0 ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
93 lines
2.8 KiB
C
93 lines
2.8 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_A38X_H
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#define _DDR3_A38X_H
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#define MAX_INTERFACE_NUM 1
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#define MAX_BUS_NUM 5
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#include "ddr3_hws_hw_training_def.h"
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#define ECC_SUPPORT
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/* right now, we're not supporting this in mainline */
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#undef SUPPORT_STATIC_DUNIT_CONFIG
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/* Controler bus divider 1 for 32 bit, 2 for 64 bit */
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#define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1
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/* Tune internal training params values */
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#define TUNE_TRAINING_PARAMS_CK_DELAY 160
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#define TUNE_TRAINING_PARAMS_CK_DELAY_16 160
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#define TUNE_TRAINING_PARAMS_PFINGER 41
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#define TUNE_TRAINING_PARAMS_NFINGER 43
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#define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xa
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#define MARVELL_BOARD MARVELL_BOARD_ID_BASE
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#define REG_DEVICE_SAR1_ADDR 0xe4204
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
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/* DRAM Windows */
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#define REG_XBAR_WIN_5_CTRL_ADDR 0x20050
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#define REG_XBAR_WIN_5_BASE_ADDR 0x20054
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/* DRAM Windows */
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#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
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#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
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#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
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#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
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#define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0
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#define REG_XBAR_WIN_16_BASE_ADDR 0x200d4
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#define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc
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#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
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#define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win))
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#define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win))
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/* SatR defined too change topology busWidth and ECC configuration */
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#define DDR_SATR_CONFIG_MASK_WIDTH 0x8
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#define DDR_SATR_CONFIG_MASK_ECC 0x10
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#define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20
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#define REG_SAMPLE_RESET_HIGH_ADDR 0x18600
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#define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ
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/* Matrix enables DRAM modes (bus width/ECC) per boardId */
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#define TOPOLOGY_UPDATE_32BIT 0
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#define TOPOLOGY_UPDATE_32BIT_ECC 1
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#define TOPOLOGY_UPDATE_16BIT 2
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#define TOPOLOGY_UPDATE_16BIT_ECC 3
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#define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4
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#define TOPOLOGY_UPDATE { \
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/* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
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{1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \
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{1, 1, 1, 1, 1}, /* DB_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \
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{0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \
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{1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \
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};
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enum {
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CPU_1066MHZ_DDR_400MHZ,
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CPU_RESERVED_DDR_RESERVED0,
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CPU_667MHZ_DDR_667MHZ,
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CPU_800MHZ_DDR_800MHZ,
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CPU_RESERVED_DDR_RESERVED1,
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CPU_RESERVED_DDR_RESERVED2,
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CPU_RESERVED_DDR_RESERVED3,
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LAST_FREQ
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};
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#define ACTIVE_INTERFACE_MASK 0x1
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#endif /* _DDR3_A38X_H */
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