York Sun 8936691ba6 driver/ddr/fsl: Fix timing_cfg_2 ... Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>		2016-08-02 09:47:34 -07:00
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altera	ddr: altera: Repair DQ window centering code	2016-04-20 11:28:45 +02:00
fsl	driver/ddr/fsl: Fix timing_cfg_2	2016-08-02 09:47:34 -07:00
marvell	arm: mvebu: a38x: Weed out floating point use	2016-05-20 11:01:00 +02:00
microchip	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.	2016-02-01 22:14:01 +01:00