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206ad6c7b0
Introduce the new board, define every bits. Tested-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
78 lines
1.5 KiB
Text
78 lines
1.5 KiB
Text
menu "Xtensa architecture"
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depends on XTENSA
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config SYS_ARCH
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string
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default "xtensa"
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config SYS_CPU
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string "Xtensa Core Variant"
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choice
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prompt "Target select"
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config TARGET_XTFPGA
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bool "Support XTFPGA"
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select BOARD_POSTCLK_INIT
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config TARGET_QEMU_XTENSA
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bool "Support QEMU Xtensa Virt Board"
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select BOARD_LATE_INIT
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endchoice
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config SYS_ICACHE_OFF
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bool "Do not enable icache"
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help
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Do not enable instruction cache in U-Boot.
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config SPL_SYS_ICACHE_OFF
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bool "Do not enable icache in SPL"
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depends on SPL
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default SYS_ICACHE_OFF
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help
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Do not enable instruction cache in SPL.
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config SYS_DCACHE_OFF
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bool "Do not enable dcache"
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help
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Do not enable data cache in U-Boot.
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config SPL_SYS_DCACHE_OFF
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bool "Do not enable dcache in SPL"
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depends on SPL
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default SYS_DCACHE_OFF
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help
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Do not enable data cache in SPL.
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config XTENSA_SEMIHOSTING
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bool "Support semihosting"
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help
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Enable Xtensa semihosting debugging support.
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choice
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prompt "Semihosting interface"
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default XTENSA_SIMCALL_ISS
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depends on XTENSA_SEMIHOSTING
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help
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Choose semihosting interface that will be used for serial port,
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block device and networking.
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config XTENSA_SIMCALL_ISS
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bool "simcall"
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help
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Use simcall instruction. simcall is only available on simulators,
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it does nothing on hardware.
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config XTENSA_SIMCALL_GDBIO
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bool "GDBIO"
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help
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Use break instruction. It is available on real hardware when GDB
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is attached to it via JTAG.
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endchoice
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source "board/cadence/xtfpga/Kconfig"
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source "board/emulation/qemu-xtensa/Kconfig"
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endmenu
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