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91069320a5
The existing pinctrl driver available for Tegra SOC is well designed, but it lacks DM support. Let's add a DM compatible overlay, which allows use of the device tree, along with preserving backward compatibility with all existing setups and the ability to use it in SPL board configuration stage. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
248 lines
6.9 KiB
C
248 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2023
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* Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <stdlib.h>
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#include <asm/arch/pinmux.h>
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static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
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{
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struct pmux_drvgrp_config *drive_group;
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int i, ret, pad_id;
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const char **pads;
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drive_group = kmalloc_array(drvcnt, sizeof(*drive_group), GFP_KERNEL);
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if (!drive_group) {
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log_debug("%s: cannot allocate drive group array\n", __func__);
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return;
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}
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drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0);
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drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0);
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drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0);
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drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0);
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#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
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drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0);
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
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drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_HSM
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drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
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#endif
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for (i = 1; i < drvcnt; i++)
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memcpy(&drive_group[i], &drive_group[0], sizeof(drive_group[0]));
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ret = dev_read_string_list(config, "nvidia,pins", &pads);
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if (ret < 0) {
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log_debug("%s: could not parse property nvidia,pins\n", __func__);
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goto exit;
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}
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for (i = 0; i < drvcnt; i++) {
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for (pad_id = 0; pad_id < PMUX_DRVGRP_COUNT; pad_id++)
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if (tegra_pinctrl_to_drvgrp[pad_id])
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if (!strcmp(pads[i], tegra_pinctrl_to_drvgrp[pad_id])) {
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drive_group[i].drvgrp = pad_id;
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break;
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}
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debug("%s drvmap: %d, %d, %d, %d, %d\n", pads[i],
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drive_group[i].drvgrp, drive_group[i].slwf,
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drive_group[i].slwr, drive_group[i].drvup,
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drive_group[i].drvdn);
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}
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pinmux_config_drvgrp_table(drive_group, drvcnt);
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free(pads);
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exit:
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kfree(drive_group);
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}
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static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
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{
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struct pmux_pingrp_config *pinmux_group;
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int i, ret, pin_id;
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const char *function;
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const char **pins;
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pinmux_group = kmalloc_array(pincnt, sizeof(*pinmux_group), GFP_KERNEL);
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if (!pinmux_group) {
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log_debug("%s: cannot allocate pinmux group array\n", __func__);
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return;
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}
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/* decode function id and fill the first copy of pmux_pingrp_config */
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function = dev_read_string(config, "nvidia,function");
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if (function)
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for (i = 0; i < PMUX_FUNC_COUNT; i++)
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if (tegra_pinctrl_to_func[i])
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if (!strcmp(function, tegra_pinctrl_to_func[i]))
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break;
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pinmux_group[0].func = i;
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pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0);
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pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0);
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#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
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pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_LOCK
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pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_OD
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pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
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pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
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pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
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pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
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pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_HSM
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pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
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#endif
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for (i = 1; i < pincnt; i++)
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memcpy(&pinmux_group[i], &pinmux_group[0], sizeof(pinmux_group[0]));
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ret = dev_read_string_list(config, "nvidia,pins", &pins);
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if (ret < 0) {
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log_debug("%s: could not parse property nvidia,pins\n", __func__);
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goto exit;
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}
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for (i = 0; i < pincnt; i++) {
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for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
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if (tegra_pinctrl_to_pingrp[pin_id])
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if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) {
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pinmux_group[i].pingrp = pin_id;
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break;
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}
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debug("%s pinmap: %d, %d, %d, %d\n", pins[i],
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pinmux_group[i].pingrp, pinmux_group[i].func,
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pinmux_group[i].pull, pinmux_group[i].tristate);
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}
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pinmux_config_pingrp_table(pinmux_group, pincnt);
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free(pins);
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exit:
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kfree(pinmux_group);
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}
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static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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struct udevice *child;
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int ret;
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const char *name;
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device_foreach_child(child, config) {
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/* Pinmux node can contain pins and drives */
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ret = dev_read_string_index(child, "nvidia,pins", 0,
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&name);
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if (ret < 0) {
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log_debug("%s: could not parse property nvidia,pins\n", __func__);
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return ret;
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}
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ret = dev_read_string_count(child, "nvidia,pins");
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if (ret < 0) {
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log_debug("%s: could not count nvidia,pins\n", __func__);
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return ret;
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}
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if (!strncmp(name, "drive_", 6))
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/* Drive node is detected */
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tegra_pinctrl_set_drive(child, ret);
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else
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/* Pin node is detected */
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tegra_pinctrl_set_pin(child, ret);
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}
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return 0;
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}
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static int tegra_pinctrl_get_pins_count(struct udevice *dev)
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{
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return PMUX_PINGRP_COUNT;
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}
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static const char *tegra_pinctrl_get_pin_name(struct udevice *dev,
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unsigned int selector)
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{
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return tegra_pinctrl_to_pingrp[selector];
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}
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static int tegra_pinctrl_get_groups_count(struct udevice *dev)
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{
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return PMUX_DRVGRP_COUNT;
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}
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static const char *tegra_pinctrl_get_group_name(struct udevice *dev,
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unsigned int selector)
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{
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return tegra_pinctrl_to_drvgrp[selector];
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}
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static int tegra_pinctrl_get_functions_count(struct udevice *dev)
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{
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return PMUX_FUNC_COUNT;
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}
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static const char *tegra_pinctrl_get_function_name(struct udevice *dev,
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unsigned int selector)
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{
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return tegra_pinctrl_to_func[selector];
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}
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const struct pinctrl_ops tegra_pinctrl_ops = {
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.get_pins_count = tegra_pinctrl_get_pins_count,
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.get_pin_name = tegra_pinctrl_get_pin_name,
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.get_groups_count = tegra_pinctrl_get_groups_count,
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.get_group_name = tegra_pinctrl_get_group_name,
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.get_functions_count = tegra_pinctrl_get_functions_count,
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.get_function_name = tegra_pinctrl_get_function_name,
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.set_state = tegra_pinctrl_set_state,
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};
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static int tegra_pinctrl_bind(struct udevice *dev)
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{
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/*
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* Make sure that the pinctrl driver gets probed after binding
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* to provide initial configuration and assure that further
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* probed devices are working correctly.
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*/
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dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
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return 0;
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}
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static const struct udevice_id tegra_pinctrl_ids[] = {
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{ .compatible = "nvidia,tegra30-pinmux" },
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{ .compatible = "nvidia,tegra114-pinmux" },
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{ },
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};
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U_BOOT_DRIVER(tegra_pinctrl) = {
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.name = "tegra_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = tegra_pinctrl_ids,
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.bind = tegra_pinctrl_bind,
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.ops = &tegra_pinctrl_ops,
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};
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