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3f190c55a4
Add socfpga_dtreg driver enablement for Intel SoCFPGA. Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
80 lines
3 KiB
Text
80 lines
3 KiB
Text
* Firewall and privilege register settings in device tree
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Required properties:
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--------------------
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- compatible: should contain "intel,socfpga-dtreg"
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- reg: Physical base address and size of block register.
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- intel,offset-settings: 32-bit offset address of block register,
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followed by 32-bit value settings and
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the masking bits, only masking bit
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set to 1 allows modification.
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The device tree node which describes secure and privilege register access
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configuration in compile time.
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Most of these registers are expected to work except for the case which some
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registers configuration are required for granting access to some other
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registers, for example CCU registers have to be properly configured before
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allowing register configuration access to fpga2sdram firewall as shown in
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below example.
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Some registers depend on runtime data for proper configuration are expected
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to be part of driver that generating these data for example configuration for
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soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from
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memory device tree node.
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Please refer details of tested examples below for both fpga2sdram and QoS
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configuration with default reset value and the comments.
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Example:
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--------
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Configuration for multiple dtreg node support in device tree:
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socfpga_dtreg0: socfpga-dtreg0 {
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compatible = "intel,socfpga-dtreg";
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#address-cells = <1>;
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#size-cells = <1>;
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bootph-all;
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coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
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reg = <0xf7100200 0x00000014>;
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intel,offset-settings =
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/*
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* Disable ocram security at CCU for
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* non secure access
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*/
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<0x0000004 0x8000ffff 0xe007ffff>,
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<0x0000008 0x8000ffff 0xe007ffff>,
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<0x000000c 0x8000ffff 0xe007ffff>,
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<0x0000010 0x8000ffff 0xe007ffff>;
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bootph-all;
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};
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};
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socfpga_dtreg1: socfpga-dtreg1 {
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compatible = "intel,socfpga-dtreg";
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#address-cells = <1>;
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#size-cells = <1>;
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bootph-all;
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soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
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reg = <0xf8020000 0x0000001c>;
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intel,offset-settings =
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/* Disable MPFE firewall for SMMU */
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<0x00000000 0x00010101 0x00010101>,
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/*
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* Disable MPFE firewall for HMC
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* adapter
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*/
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<0x00000004 0x00000001 0x00010101>;
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bootph-all;
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};
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};
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To call the nodes use:
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ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg0", &dev);
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ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg1", &dev);
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