mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-24 22:36:05 +00:00
4b0ea24b42
This patch has the goal to add support for DesignWare UFS Controller specific operations. This is based on linux kernel commit: "drivers/scsi/ufs/ufshcd-dwc.c: ufs: add support for DesignWare Controller" (sha1: 4b9ffb5a353bdee49f1f477ffe2b95ab3f9cbc0c) It is ported from linux kernel 6.11-rc1. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240920041651.18173-2-venkatesh.abbarapu@amd.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
32 lines
705 B
C
32 lines
705 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* UFS Host driver for Synopsys Designware Core
|
|
*
|
|
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* Authors: Joao Pinto <jpinto@synopsys.com>
|
|
*/
|
|
|
|
#ifndef _UFSHCI_DWC_H
|
|
#define _UFSHCI_DWC_H
|
|
|
|
/* DWC HC UFSHCI specific Registers */
|
|
enum dwc_specific_registers {
|
|
DWC_UFS_REG_HCLKDIV = 0xFC,
|
|
};
|
|
|
|
/* Clock Divider Values: Hex equivalent of frequency in MHz */
|
|
enum clk_div_values {
|
|
DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
|
|
DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
|
|
DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
|
|
};
|
|
|
|
/* Selector Index */
|
|
enum selector_index {
|
|
SELIND_LN0_TX = 0x00,
|
|
SELIND_LN1_TX = 0x01,
|
|
SELIND_LN0_RX = 0x04,
|
|
SELIND_LN1_RX = 0x05,
|
|
};
|
|
#endif
|