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7366aacf8e
Add Renesas R-Car Gen4 DBSC5 DRAM controller driver. This driver is currently capable of bringing LPDDR5 DRAM on Renesas R-Car V4H Whitehawk board. Further boards can be supported by supplying board specific DRAM configuration data via dbsc5_get_board_data(). Support for R-Car V4M is not implemented, however the driver is already mostly prepared to support this SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <errno.h>
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#include <ram.h>
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#include <linux/sizes.h>
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/* RT-VRAM register base address */
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#define RTVRAM_VBUF_CFG 0x6504
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#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1 << 8)
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#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6 << 0)
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#define RTVRAM_EXT_MODE 0x8500
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#define RTVRAM_EXT_MODE_EXT BIT(0)
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#define RTVRAM_VBUF_BADDR 0xC580
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#define RTVRAM_VBUF_NUM 7
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#define SDRAM_40BIT_ADDR_TOP 0x0400000000ULL
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#define RTVRAM_VBUF_AREA_SIZE SZ_4M
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struct renesas_dbsc5_rtvram_priv {
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void __iomem *regs;
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};
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static int renesas_dbsc5_rtvram_probe(struct udevice *dev)
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{
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struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
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u64 addr;
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int i;
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/* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */
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for (i = 0; i < RTVRAM_VBUF_NUM; i++) {
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addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16;
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writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i)));
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}
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/* Cache Mode: 8-way, VBF size: 28M */
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setbits_le32(priv->regs + RTVRAM_VBUF_CFG,
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RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M);
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/* Change from Compatible Mode to Extended Mode */
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writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE);
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dsb();
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return 0;
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}
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static int renesas_dbsc5_rtvram_of_to_plat(struct udevice *dev)
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{
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struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs)
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return -EINVAL;
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return 0;
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}
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static int renesas_dbsc5_rtvram_get_info(struct udevice *dev,
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struct ram_info *info)
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{
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struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
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info->base = (phys_addr_t)priv->regs;
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info->size = 28 * SZ_1M;
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return 0;
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}
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static const struct ram_ops renesas_dbsc5_rtvram_ops = {
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.get_info = renesas_dbsc5_rtvram_get_info,
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};
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static const struct udevice_id renesas_dbsc5_rtvram_ids[] = {
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{ .compatible = "renesas,r8a779g0-rtvram" },
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{ .compatible = "renesas,r8a779h0-rtvram" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(renesas_dbsc5_rtvram) = {
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.name = "rtvram",
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.id = UCLASS_RAM,
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.of_match = renesas_dbsc5_rtvram_ids,
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.of_to_plat = renesas_dbsc5_rtvram_of_to_plat,
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.ops = &renesas_dbsc5_rtvram_ops,
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.probe = renesas_dbsc5_rtvram_probe,
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.priv_auto = sizeof(struct renesas_dbsc5_rtvram_priv),
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};
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