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6947939b62
Add a driver for the new Synopsys eUSB2 PHY found in the SM8550 and SM8650 SoCs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
366 lines
11 KiB
C
366 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023-2024, Linaro Limited
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*
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* Based on the Linux phy-qcom-snps-eusb2.c driver
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*/
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#include <clk.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <generic-phy.h>
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#include <malloc.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#define USB_PHY_UTMI_CTRL0 (0x3c)
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#define SLEEPM BIT(0)
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#define OPMODE_MASK GENMASK(4, 3)
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#define OPMODE_NONDRIVING BIT(3)
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#define USB_PHY_UTMI_CTRL5 (0x50)
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#define POR BIT(1)
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#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
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#define PHY_ENABLE BIT(0)
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#define SIDDQ_SEL BIT(1)
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#define SIDDQ BIT(2)
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#define RETENABLEN BIT(3)
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#define FSEL_MASK GENMASK(6, 4)
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#define FSEL_19_2_MHZ_VAL (0x0)
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#define FSEL_38_4_MHZ_VAL (0x4)
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#define USB_PHY_CFG_CTRL_1 (0x58)
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#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1)
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#define USB_PHY_CFG_CTRL_2 (0x5c)
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#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0)
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#define DIV_7_0_19_2_MHZ_VAL (0x90)
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#define DIV_7_0_38_4_MHZ_VAL (0xc8)
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#define USB_PHY_CFG_CTRL_3 (0x60)
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#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
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#define DIV_11_8_19_2_MHZ_VAL (0x1)
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#define DIV_11_8_38_4_MHZ_VAL (0x0)
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#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4)
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#define PLL_REF_DIV_VAL (0x0)
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#define USB_PHY_HS_PHY_CTRL2 (0x64)
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#define VBUSVLDEXT0 BIT(0)
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#define USB2_SUSPEND_N BIT(2)
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#define USB2_SUSPEND_N_SEL BIT(3)
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#define VBUS_DET_EXT_SEL BIT(4)
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#define USB_PHY_CFG_CTRL_4 (0x68)
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#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)
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#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)
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#define USB_PHY_CFG_CTRL_5 (0x6c)
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#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0)
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#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)
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#define USB_PHY_CFG_CTRL_6 (0x70)
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#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)
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#define USB_PHY_CFG_CTRL_7 (0x74)
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#define USB_PHY_CFG_CTRL_8 (0x78)
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#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)
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#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2)
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#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3)
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#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
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#define USB_PHY_CFG_CTRL_9 (0x7c)
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#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0)
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#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3)
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#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5)
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#define PHY_CFG_RCAL_BYPASS BIT(7)
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#define USB_PHY_CFG_CTRL_10 (0x80)
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#define USB_PHY_CFG0 (0x94)
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#define DATAPATH_CTRL_OVERRIDE_EN BIT(0)
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#define CMN_CTRL_OVERRIDE_EN BIT(1)
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#define UTMI_PHY_CMN_CTRL0 (0x98)
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#define TESTBURNIN BIT(6)
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#define USB_PHY_FSEL_SEL (0xb8)
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#define FSEL_SEL BIT(0)
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#define USB_PHY_APB_ACCESS_CMD (0x130)
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#define RW_ACCESS BIT(0)
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#define APB_START_CMD BIT(1)
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#define APB_LOGIC_RESET BIT(2)
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#define USB_PHY_APB_ACCESS_STATUS (0x134)
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#define ACCESS_DONE BIT(0)
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#define TIMED_OUT BIT(1)
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#define ACCESS_ERROR BIT(2)
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#define ACCESS_IN_PROGRESS BIT(3)
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#define USB_PHY_APB_ADDRESS (0x138)
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#define APB_REG_ADDR_MASK GENMASK(7, 0)
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#define USB_PHY_APB_WRDATA_LSB (0x13c)
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#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0)
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#define USB_PHY_APB_WRDATA_MSB (0x140)
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#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4)
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#define USB_PHY_APB_RDDATA_LSB (0x144)
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#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0)
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#define USB_PHY_APB_RDDATA_MSB (0x148)
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#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4)
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struct qcom_snps_eusb2_phy_priv {
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void __iomem *base;
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struct clk *ref_clk;
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struct reset_ctl_bulk resets;
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};
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static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset,
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u32 mask, u32 val)
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{
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u32 reg;
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reg = readl_relaxed(base + offset);
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reg &= ~mask;
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reg |= val & mask;
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writel_relaxed(reg, base + offset);
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/* Ensure above write is completed */
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readl_relaxed(base + offset);
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}
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static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2)
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{
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/* default parameters: tx pre-emphasis */
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9,
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PHY_CFG_TX_PREEMP_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0));
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/* tx rise/fall time */
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9,
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PHY_CFG_TX_RISE_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2));
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/* source impedance adjustment */
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9,
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PHY_CFG_TX_RES_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1));
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/* dc voltage level adjustement */
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_8,
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PHY_CFG_TX_HS_VREF_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3));
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/* transmitter HS crossover adjustement */
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_8,
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PHY_CFG_TX_HS_XV_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0));
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}
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static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2)
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{
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unsigned long ref_clk_freq = clk_get_rate(qcom_snps_eusb2->ref_clk);
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switch (ref_clk_freq) {
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case 19200000:
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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FSEL_MASK,
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FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_2,
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PHY_CFG_PLL_FB_DIV_7_0_MASK,
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DIV_7_0_19_2_MHZ_VAL);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_3,
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PHY_CFG_PLL_FB_DIV_11_8_MASK,
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DIV_11_8_19_2_MHZ_VAL);
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break;
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case 38400000:
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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FSEL_MASK,
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FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_2,
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PHY_CFG_PLL_FB_DIV_7_0_MASK,
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DIV_7_0_38_4_MHZ_VAL);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_3,
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PHY_CFG_PLL_FB_DIV_11_8_MASK,
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DIV_11_8_38_4_MHZ_VAL);
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break;
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default:
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printf("%s: unsupported ref_clk_freq:%lu\n", __func__, ref_clk_freq);
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return -EINVAL;
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}
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_3,
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PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);
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return 0;
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}
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static int qcom_snps_eusb2_usb_init(struct phy *phy)
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{
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struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(phy->dev);
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int ret;
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG0,
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CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_UTMI_CTRL5, POR, POR);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_APB_ACCESS_CMD,
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APB_LOGIC_RESET, APB_LOGIC_RESET);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_FSEL_SEL,
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FSEL_SEL, FSEL_SEL);
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/* update ref_clk related registers */
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ret = qcom_eusb2_ref_clk_init(qcom_snps_eusb2);
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if (ret)
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return ret;
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_1,
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PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_4,
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PHY_CFG_PLL_INT_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_4,
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PHY_CFG_PLL_GMP_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_5,
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PHY_CFG_PLL_PROP_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_6,
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PHY_CFG_PLL_VCO_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_5,
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PHY_CFG_PLL_VREF_TUNE_MASK,
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FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1));
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL2,
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VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL);
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/* set default parameters */
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qcom_eusb2_default_parameters(qcom_snps_eusb2);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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SIDDQ_SEL, SIDDQ_SEL);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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SIDDQ, 0);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_UTMI_CTRL5, POR, 0);
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qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N_SEL, 0);
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return 0;
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}
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static int qcom_snps_eusb2_phy_power_on(struct phy *phy)
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{
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struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(phy->dev);
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int ret;
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/* TODO Repeater */
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clk_prepare_enable(qcom_snps_eusb2->ref_clk);
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ret = reset_deassert_bulk(&qcom_snps_eusb2->resets);
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if (ret)
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return ret;
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ret = qcom_snps_eusb2_usb_init(phy);
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if (ret)
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return ret;
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return 0;
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}
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static int qcom_snps_eusb2_phy_power_off(struct phy *phy)
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{
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struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(phy->dev);
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reset_assert_bulk(&qcom_snps_eusb2->resets);
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clk_disable_unprepare(qcom_snps_eusb2->ref_clk);
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return 0;
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}
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static int qcom_snps_eusb2_phy_probe(struct udevice *dev)
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{
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struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(dev);
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int ret;
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qcom_snps_eusb2->base = (void __iomem *)dev_read_addr(dev);
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if (IS_ERR(qcom_snps_eusb2->base))
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return PTR_ERR(qcom_snps_eusb2->base);
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qcom_snps_eusb2->ref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(qcom_snps_eusb2->ref_clk)) {
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printf("%s: failed to get ref clk %d\n", __func__, ret);
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return PTR_ERR(qcom_snps_eusb2->ref_clk);
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}
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ret = reset_get_bulk(dev, &qcom_snps_eusb2->resets);
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if (ret < 0) {
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printf("failed to get resets, ret = %d\n", ret);
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return ret;
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}
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return 0;
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}
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static struct phy_ops qcom_snps_eusb2_phy_ops = {
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.power_on = qcom_snps_eusb2_phy_power_on,
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.power_off = qcom_snps_eusb2_phy_power_off,
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};
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static const struct udevice_id qcom_snps_eusb2_phy_ids[] = {
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{
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.compatible = "qcom,sm8550-snps-eusb2-phy",
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},
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{}
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};
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U_BOOT_DRIVER(qcom_usb_qcom_snps_eusb2) = {
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.name = "qcom-snps-eusb2-hsphy",
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.id = UCLASS_PHY,
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.of_match = qcom_snps_eusb2_phy_ids,
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.ops = &qcom_snps_eusb2_phy_ops,
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.probe = qcom_snps_eusb2_phy_probe,
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.priv_auto = sizeof(struct qcom_snps_eusb2_phy_priv),
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};
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