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https://github.com/u-boot/u-boot.git
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99d240e8fb
amba is not approved node name for simple-bus that's why use axi instead to be aligned with other xilinx boards. Node reference is not changed that's why there is no impact but also mini configuration will never gets to OS that's why nothing should be affected from OS perspective (paths in /proc/ for example). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1b18a69ae47bdcb1a0795af7621d13bfecfc9861.1726219714.git.michal.simek@amd.com
132 lines
2.9 KiB
Text
132 lines
2.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx CSE QSPI board DTS
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*
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* Copyright (C) 2015 - 2017 Xilinx, Inc.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Zynq CSE QSPI Board";
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compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
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aliases {
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spi0 = &qspi;
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serial0 = &dcc;
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};
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memory@fffc0000 {
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device_type = "memory";
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reg = <0xFFFC0000 0x40000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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bootph-all;
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};
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amba: axi {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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};
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qspi: spi@e000d000 {
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clock-names = "ref_clk", "pclk";
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clocks = <&clkc 10>, <&clkc 43>;
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compatible = "xlnx,zynq-qspi-1.0";
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status = "okay";
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interrupt-parent = <&intc>;
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interrupts = <0 19 4>;
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reg = <0xe000d000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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flash0: flash@0 {
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compatible = "n25q128a11", "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@100000 {
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@600000 {
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@620000 {
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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partition@c00000 {
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label = "qspi-bitstream";
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reg = <0xC00000 0x400000>;
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};
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};
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};
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slcr: slcr@f8000000 {
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bootph-all;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
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reg = <0xF8000000 0x1000>;
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ranges;
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clkc: clkc@100 {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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fclk-enable = <0xf>;
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bootph-all;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
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};
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};
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scutimer: timer@f8f00600 {
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bootph-all;
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xf8f00600 0x20>;
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clock-frequency = <333333333>;
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};
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};
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};
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&dcc {
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status = "okay";
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};
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