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The Lenovo IdeaPad Yoga 11 is a hybrid laptop/tablet Windows RT-based computer released in late 2012. The device uses a 1.3 GHz quad-core Nvidia Tegra 3 chipset with 2 GB of RAM, features a 11.6 inch 1366x768 screen and 32/64 GB of internal memory that can be supplemented with a microSDXC card slot, full size SD card slot and 2 full size USB 2.0 ports. Tested-by: Jethro Bull <jethrob@hotmail.com> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
1266 lines
33 KiB
Text
1266 lines
33 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "tegra30.dtsi"
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/ {
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model = "Lenovo Ideapad Yoga 11 Slate";
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compatible = "lenovo,ideapad-yoga-11", "nvidia,tegra30";
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chosen {
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stdout-path = &uarta;
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};
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aliases {
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i2c0 = &pwr_i2c;
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i2c1 = &gen2_i2c;
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mmc0 = &sdmmc4; /* eMMC */
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mmc1 = &sdmmc1; /* uSD slot */
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rtc0 = &pmic;
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rtc1 = "/rtc@7000e000";
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spi0 = &spi4;
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usb0 = &usb1;
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usb1 = &usb3;
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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};
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host1x@50000000 {
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dc@54200000 {
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rgb {
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status = "okay";
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nvidia,panel = <&bridge>;
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};
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};
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};
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pinmux@70000868 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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/* SDMMC1 pinmux */
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sdmmc1-clk {
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nvidia,pins = "sdmmc1_clk_pz0";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc1-cmd {
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nvidia,pins = "sdmmc1_dat3_py4",
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"sdmmc1_dat2_py5",
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"sdmmc1_dat1_py6",
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"sdmmc1_dat0_py7",
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"sdmmc1_cmd_pz1";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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/* SDMMC3 pinmux */
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sdmmc3-clk {
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nvidia,pins = "sdmmc3_clk_pa6";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3-cmd {
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nvidia,pins = "sdmmc3_cmd_pa7",
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"sdmmc3_dat3_pb4",
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"sdmmc3_dat2_pb5",
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"sdmmc3_dat1_pb6",
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"sdmmc3_dat0_pb7";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3-dat6 {
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nvidia,pins = "sdmmc3_dat6_pd3";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3-dat7 {
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nvidia,pins = "sdmmc3_dat7_pd4";
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nvidia,function = "spdif";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* SDMMC4 pinmux */
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sdmmc4-clk {
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nvidia,pins = "sdmmc4_clk_pcc4";
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nvidia,function = "sdmmc4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,lock = <1>;
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nvidia,io-reset = <1>;
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};
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sdmmc4-cmd {
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nvidia,pins = "sdmmc4_cmd_pt7",
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"sdmmc4_dat0_paa0",
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"sdmmc4_dat1_paa1",
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"sdmmc4_dat2_paa2",
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"sdmmc4_dat3_paa3",
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"sdmmc4_dat4_paa4",
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"sdmmc4_dat5_paa5",
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"sdmmc4_dat6_paa6",
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"sdmmc4_dat7_paa7",
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"sdmmc4_rst_n_pcc3";
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nvidia,function = "sdmmc4";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,lock = <1>;
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nvidia,io-reset = <1>;
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};
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cam-mclk {
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nvidia,pins = "cam_mclk_pcc0";
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nvidia,function = "vi_alt3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* I2C pinmux */
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gen1-i2c {
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nvidia,pins = "gen1_i2c_scl_pc4",
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"gen1_i2c_sda_pc5";
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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nvidia,lock = <1>;
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};
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gen2-i2c {
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nvidia,pins = "gen2_i2c_scl_pt5",
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"gen2_i2c_sda_pt6";
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nvidia,function = "i2c2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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nvidia,lock = <1>;
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};
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cam-i2c {
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nvidia,pins = "cam_i2c_scl_pbb1",
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"cam_i2c_sda_pbb2";
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nvidia,function = "i2c3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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nvidia,lock = <1>;
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};
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ddc-i2c {
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nvidia,pins = "ddc_scl_pv4",
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"ddc_sda_pv5";
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nvidia,function = "i2c4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,lock = <1>;
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};
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pwr-i2c {
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nvidia,pins = "pwr_i2c_scl_pz6",
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"pwr_i2c_sda_pz7";
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nvidia,function = "i2cpwr";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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nvidia,lock = <1>;
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};
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/* HDMI pinmux */
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hdmi-cec {
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nvidia,pins = "hdmi_cec_pee3";
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nvidia,function = "cec";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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hdmi-int {
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nvidia,pins = "hdmi_int_pn7";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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/* UART-A */
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ulpi-data0 {
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nvidia,pins = "ulpi_data0_po1";
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nvidia,function = "uarta";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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ulpi-data1 {
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nvidia,pins = "ulpi_data1_po2";
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nvidia,function = "uarta";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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ulpi-data2 {
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nvidia,pins = "ulpi_data2_po3";
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nvidia,function = "uarta";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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/* UART-B */
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uartb-txd-rxd {
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nvidia,pins = "uart2_txd_pc2",
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"uart2_rxd_pc3";
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nvidia,function = "uartb";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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uartb-cts-rts {
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nvidia,pins = "uart2_cts_n_pj5",
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"uart2_rts_n_pj6";
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nvidia,function = "gmi";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* UART-C */
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uartc-rxd-cts {
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nvidia,pins = "uart3_cts_n_pa1",
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"uart3_rxd_pw7";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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uartc-txd-rts {
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nvidia,pins = "uart3_rts_n_pc0",
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"uart3_txd_pw6";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* I2S pinmux */
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dap1-fs {
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nvidia,pins = "dap1_fs_pn0";
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nvidia,function = "i2s0";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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dap1-din {
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nvidia,pins = "dap1_din_pn1",
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"dap1_dout_pn2",
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"dap1_sclk_pn3";
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nvidia,function = "i2s0";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap2-fs-pa2 {
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nvidia,pins = "dap2_fs_pa2",
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"dap2_sclk_pa3",
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"dap2_din_pa4",
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"dap2_dout_pa5";
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap3-fs-pp0 {
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nvidia,pins = "dap3_fs_pp0",
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"dap3_din_pp1",
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"dap3_dout_pp2";
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nvidia,function = "i2s2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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dap3-sclk-pp3 {
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nvidia,pins = "dap3_sclk_pp3";
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nvidia,function = "i2s2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap4-fs-pp4 {
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nvidia,pins = "dap4_fs_pp4",
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"dap4_din_pp5",
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"dap4_dout_pp6",
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"dap4_sclk_pp7";
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nvidia,function = "i2s3";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pbb0 {
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nvidia,pins = "pbb0", "pbb7";
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nvidia,function = "i2s4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pcc1 {
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nvidia,pins = "pcc1";
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nvidia,function = "i2s4";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pcc2 {
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nvidia,pins = "pcc2";
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nvidia,function = "i2s4";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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/* PCI-e pinmux */
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pex-l2-rst-n {
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nvidia,pins = "pex_l2_rst_n_pcc6",
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"pex_l2_clkreq_n_pcc7",
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"pex_l0_prsnt_n_pdd0",
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"pex_l0_rst_n_pdd1",
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"pex_l0_clkreq_n_pdd2",
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"pex_wake_n_pdd3",
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"pex_l1_prsnt_n_pdd4",
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"pex_l1_rst_n_pdd5",
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"pex_l1_clkreq_n_pdd6",
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"pex_l2_prsnt_n_pdd7";
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nvidia,function = "pcie";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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/* SPI pinmux */
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spi1-miso-px7 {
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nvidia,pins = "spi1_miso_px7";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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ulpi-clk-py0 {
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nvidia,pins = "ulpi_clk_py0",
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"ulpi_dir_py1",
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"ulpi_nxt_py2",
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"ulpi_stp_py3";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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ulpi-data7-po0 {
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nvidia,pins = "ulpi_data7_po0",
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"ulpi_data5_po6",
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"ulpi_data6_po7",
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"spi1_mosi_px4",
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"spi1_sck_px5";
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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ulpi-data4-po5 {
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nvidia,pins = "ulpi_data4_po5";
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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spi1-cs0-n-px6 {
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nvidia,pins = "spi1_cs0_n_px6";
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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ulpi-data3-po4 {
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nvidia,pins = "ulpi_data3_po4";
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nvidia,function = "spi3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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spi2-cs1-n-pw2 {
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nvidia,pins = "spi2_cs1_n_pw2",
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"spi2_cs2_n_pw3";
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nvidia,function = "spi3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gmi-a17-pb0 {
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nvidia,pins = "gmi_a17_pb0",
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"gmi_a18_pb1",
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"gmi_a16_pj7",
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"gmi_a19_pk7";
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nvidia,function = "spi4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
spi2-mosi-px0 {
|
|
nvidia,pins = "spi2_mosi_px0";
|
|
nvidia,function = "spi6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
spi2-miso-px1 {
|
|
nvidia,pins = "spi2_miso_px1";
|
|
nvidia,function = "spi6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
spi2-sck-px2 {
|
|
nvidia,pins = "spi2_sck_px2";
|
|
nvidia,function = "spi6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Display A pinmux */
|
|
lcd-pclk {
|
|
nvidia,pins = "lcd_pclk_pb3",
|
|
"lcd_dc1_pd2",
|
|
"lcd_d0_pe0",
|
|
"lcd_d1_pe1",
|
|
"lcd_d2_pe2",
|
|
"lcd_d3_pe3",
|
|
"lcd_d4_pe4",
|
|
"lcd_d5_pe5",
|
|
"lcd_d6_pe6",
|
|
"lcd_d7_pe7",
|
|
"lcd_d8_pf0",
|
|
"lcd_d9_pf1",
|
|
"lcd_d10_pf2",
|
|
"lcd_d11_pf3",
|
|
"lcd_d12_pf4",
|
|
"lcd_d13_pf5",
|
|
"lcd_d14_pf6",
|
|
"lcd_d15_pf7",
|
|
"lcd_de_pj1",
|
|
"lcd_d16_pm0",
|
|
"lcd_d17_pm1",
|
|
"lcd_d18_pm2",
|
|
"lcd_d19_pm3",
|
|
"lcd_d20_pm4",
|
|
"lcd_d21_pm5",
|
|
"lcd_d22_pm6",
|
|
"lcd_d23_pm7",
|
|
"lcd_sdout_pn5",
|
|
"lcd_dc0_pn6",
|
|
"lcd_m1_pw1",
|
|
"lcd_sdin_pz2",
|
|
"lcd_sck_pz4";
|
|
nvidia,function = "displaya";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd-pwr0 {
|
|
nvidia,pins = "lcd_pwr0_pb2",
|
|
"lcd_pwr2_pc6";
|
|
nvidia,function = "displaya";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd-pwr1 {
|
|
nvidia,pins = "lcd_pwr1_pc1";
|
|
nvidia,function = "displaya";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
lcd-hsync {
|
|
nvidia,pins = "lcd_hsync_pj3",
|
|
"lcd_vsync_pj4",
|
|
"lcd_cs0_n_pn4",
|
|
"lcd_cs1_n_pw0",
|
|
"lcd_wr_n_pz3";
|
|
nvidia,function = "displaya";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
crt-hsync-pv6 {
|
|
nvidia,pins = "crt_hsync_pv6",
|
|
"crt_vsync_pv7";
|
|
nvidia,function = "crt";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
blink {
|
|
nvidia,pins = "clk_32k_out_pa0";
|
|
nvidia,function = "blink";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* KBC keys */
|
|
kb-pins {
|
|
nvidia,pins = "kb_col0_pq0",
|
|
"kb_col1_pq1",
|
|
"kb_col2_pq2",
|
|
"kb_col3_pq3",
|
|
"kb_col4_pq4",
|
|
"kb_col5_pq5",
|
|
"kb_col6_pq6",
|
|
"kb_col7_pq7",
|
|
"kb_row0_pr0",
|
|
"kb_row1_pr1",
|
|
"kb_row2_pr2",
|
|
"kb_row3_pr3",
|
|
"kb_row4_pr4",
|
|
"kb_row5_pr5",
|
|
"kb_row6_pr6",
|
|
"kb_row7_pr7",
|
|
"kb_row8_ps0",
|
|
"kb_row9_ps1",
|
|
"kb_row10_ps2",
|
|
"kb_row11_ps3",
|
|
"kb_row12_ps4",
|
|
"kb_row13_ps5",
|
|
"kb_row14_ps6",
|
|
"kb_row15_ps7";
|
|
nvidia,function = "kbc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* SPDIF pinmux */
|
|
spdif-pins {
|
|
nvidia,pins = "spdif_out_pk5",
|
|
"spdif_in_pk6";
|
|
nvidia,function = "spdif";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
jtag-rtck {
|
|
nvidia,pins = "jtag_rtck_pu7";
|
|
nvidia,function = "rtck";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* GMI pinmux */
|
|
gmi-wp-n-pc7 {
|
|
nvidia,pins = "gmi_wp_n_pc7";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3-dat5-pd0 {
|
|
nvidia,pins = "sdmmc3_dat5_pd0",
|
|
"gmi_ad8_ph0";
|
|
nvidia,function = "pwm0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3-dat4-pd1 {
|
|
nvidia,pins = "sdmmc3_dat4_pd1";
|
|
nvidia,function = "pwm1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gmi-ad12-ph4 {
|
|
nvidia,pins = "gmi_ad12_ph4",
|
|
"gmi_cs4_n_pk2",
|
|
"pv1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-dqs-pi2 {
|
|
nvidia,pins = "gmi_dqs_pi2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-ad13-ph5 {
|
|
nvidia,pins = "gmi_ad13_ph5",
|
|
"gmi_ad14_ph6",
|
|
"pu1",
|
|
"pu2",
|
|
"pv2",
|
|
"pv3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gmi-ad0-pg0 {
|
|
nvidia,pins = "gmi_ad0_pg0",
|
|
"gmi_ad1_pg1",
|
|
"gmi_ad2_pg2",
|
|
"gmi_ad3_pg3",
|
|
"gmi_ad4_pg4",
|
|
"gmi_ad5_pg5",
|
|
"gmi_ad6_pg6",
|
|
"gmi_ad7_pg7",
|
|
"gmi_ad15_ph7";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-ad9-ph1 {
|
|
nvidia,pins = "gmi_ad9_ph1";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-ad10-ph2 {
|
|
nvidia,pins = "gmi_ad10_ph2";
|
|
nvidia,function = "pwm2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gmi-ad11-ph3 {
|
|
nvidia,pins = "gmi_ad11_ph3";
|
|
nvidia,function = "pwm3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gmi-wr-n-pi0 {
|
|
nvidia,pins = "gmi_wr_n_pi0",
|
|
"gmi_oe_n_pi1",
|
|
"gmi_adv_n_pk0",
|
|
"gmi_clk_pk1";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-cs6-n-pi3 {
|
|
nvidia,pins = "gmi_cs6_n_pi3",
|
|
"gmi_cs7_n_pi6";
|
|
nvidia,function = "nand";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-iordy-pi5 {
|
|
nvidia,pins = "gmi_iordy_pi5";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-wait-pi7 {
|
|
nvidia,pins = "gmi_wait_pi7";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-cs0-n-pj0 {
|
|
nvidia,pins = "gmi_cs0_n_pj0",
|
|
"gmi_cs1_n_pj2",
|
|
"gmi_cs2_n_pk3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gmi-cs3-n-pk4 {
|
|
nvidia,pins = "gmi_cs3_n_pk4",
|
|
"pv0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* VI pinmux */
|
|
vi-d1-pd5 {
|
|
nvidia,pins = "vi_d1_pd5";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <1>;
|
|
nvidia,io-reset = <1>;
|
|
};
|
|
vi-vsync-pd6 {
|
|
nvidia,pins = "vi_vsync_pd6",
|
|
"vi_d7_pl5",
|
|
"vi_d10_pt2",
|
|
"vi_d0_pt4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <1>;
|
|
nvidia,io-reset = <2>;
|
|
};
|
|
vi-hsync-pd7 {
|
|
nvidia,pins = "vi_hsync_pd7",
|
|
"vi_d6_pl4",
|
|
"vi_d8_pl6",
|
|
"vi_d9_pl7",
|
|
"vi_pclk_pt0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,lock = <1>;
|
|
nvidia,io-reset = <1>;
|
|
};
|
|
vi-d2-pl0 {
|
|
nvidia,pins = "vi_d2_pl0",
|
|
"vi_d3_pl1",
|
|
"vi_d4_pl2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <1>;
|
|
nvidia,io-reset = <1>;
|
|
};
|
|
vi-mclk-pt1 {
|
|
nvidia,pins = "vi_mclk_pt1";
|
|
nvidia,function = "vi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <1>;
|
|
nvidia,io-reset = <2>;
|
|
};
|
|
vi-d11-pt3 {
|
|
nvidia,pins = "vi_d11_pt3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <1>;
|
|
nvidia,io-reset = <1>;
|
|
};
|
|
vi-d5-pl3 {
|
|
nvidia,pins = "vi_d5_pl3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <1>;
|
|
nvidia,io-reset = <1>;
|
|
};
|
|
|
|
/* PORT U */
|
|
pu0 {
|
|
nvidia,pins = "pu0";
|
|
nvidia,function = "owr";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pu3 {
|
|
nvidia,pins = "pu3";
|
|
nvidia,function = "pwm0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pu4 {
|
|
nvidia,pins = "pu4";
|
|
nvidia,function = "pwm1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pu5 {
|
|
nvidia,pins = "pu5";
|
|
nvidia,function = "pwm2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu6 {
|
|
nvidia,pins = "pu6";
|
|
nvidia,function = "pwm3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* PORT BB */
|
|
pbb3 {
|
|
nvidia,pins = "pbb3";
|
|
nvidia,function = "vgp3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb4 {
|
|
nvidia,pins = "pbb4";
|
|
nvidia,function = "vgp4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb5 {
|
|
nvidia,pins = "pbb5";
|
|
nvidia,function = "vgp5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pbb6 {
|
|
nvidia,pins = "pbb6";
|
|
nvidia,function = "vgp6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* CLK pinmux */
|
|
clk1-out {
|
|
nvidia,pins = "clk1_out_pw4";
|
|
nvidia,function = "extperiph1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk1-req {
|
|
nvidia,pins = "clk1_req_pee2";
|
|
nvidia,function = "dap";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk2-out {
|
|
nvidia,pins = "clk2_out_pw5";
|
|
nvidia,function = "extperiph2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk2-req {
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
nvidia,function = "dap";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk3-out {
|
|
nvidia,pins = "clk3_out_pee0";
|
|
nvidia,function = "extperiph3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk3-req {
|
|
nvidia,pins = "clk3_req_pee1";
|
|
nvidia,function = "dev3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sys-clk-req {
|
|
nvidia,pins = "sys_clk_req_pz5";
|
|
nvidia,function = "sysclk";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
owr {
|
|
nvidia,pins = "owr";
|
|
nvidia,function = "owr";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* GPIO power/drive control */
|
|
drive-sdio1 {
|
|
nvidia,pins = "drive_sdio1",
|
|
"drive_sdio3";
|
|
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
nvidia,pull-down-strength = <46>;
|
|
nvidia,pull-up-strength = <42>;
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
|
};
|
|
};
|
|
};
|
|
|
|
uarta: serial@70006000 {
|
|
status = "okay";
|
|
};
|
|
|
|
pwm: pwm@7000a000 {
|
|
status = "okay";
|
|
};
|
|
|
|
gen2_i2c: i2c@7000c400 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
|
|
bridge: dp501@8 {
|
|
compatible = "parade,dp501";
|
|
reg = <0x08>;
|
|
|
|
enable-gpios = <&gpio TEGRA_GPIO(C, 1) GPIO_ACTIVE_HIGH>;
|
|
reset-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_LOW>;
|
|
|
|
power-supply = <&vdd_edp_reg>;
|
|
|
|
panel = <&panel>;
|
|
};
|
|
};
|
|
|
|
pwr_i2c: i2c@7000d000 {
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
/* Texas Instruments TPS659110 PMIC */
|
|
pmic: tps65911@2d {
|
|
compatible = "ti,tps65911";
|
|
reg = <0x2d>;
|
|
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
|
|
ti,system-power-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
|
|
regulators {
|
|
vdd_1v8_vio: vddio {
|
|
regulator-name = "vdd_1v8_gen";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
vddio_usd: ldo3 {
|
|
regulator-name = "vddio_usd";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
spi4: spi@7000da00 {
|
|
status = "okay";
|
|
spi-max-frequency = <25000000>;
|
|
|
|
spi-flash@1 {
|
|
compatible = "winbond,w25q32", "jedec,spi-nor";
|
|
reg = <1>;
|
|
spi-max-frequency = <20000000>;
|
|
};
|
|
};
|
|
|
|
kbc@7000e200 {
|
|
status = "okay";
|
|
nvidia,debounce-delay-ms = <2>;
|
|
nvidia,repeat-delay-ms = <160>;
|
|
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
|
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
|
|
|
linux,keymap = <
|
|
MATRIX_KEY(0x00, 0x01, KEY_TAB)
|
|
MATRIX_KEY(0x00, 0x02, KEY_GRAVE)
|
|
MATRIX_KEY(0x00, 0x03, KEY_1)
|
|
MATRIX_KEY(0x00, 0x04, KEY_Q)
|
|
MATRIX_KEY(0x00, 0x05, KEY_A)
|
|
|
|
MATRIX_KEY(0x01, 0x06, KEY_RIGHTALT)
|
|
MATRIX_KEY(0x01, 0x07, KEY_LEFTALT)
|
|
|
|
MATRIX_KEY(0x02, 0x00, KEY_F3)
|
|
MATRIX_KEY(0x02, 0x01, KEY_F4)
|
|
MATRIX_KEY(0x02, 0x02, KEY_CAPSLOCK)
|
|
MATRIX_KEY(0x02, 0x03, KEY_3)
|
|
MATRIX_KEY(0x02, 0x04, KEY_E)
|
|
MATRIX_KEY(0x02, 0x05, KEY_D)
|
|
MATRIX_KEY(0x02, 0x06, KEY_C)
|
|
MATRIX_KEY(0x02, 0x07, KEY_SPACE)
|
|
|
|
MATRIX_KEY(0x03, 0x00, KEY_F2)
|
|
MATRIX_KEY(0x03, 0x01, KEY_F1)
|
|
MATRIX_KEY(0x03, 0x02, KEY_ESC)
|
|
MATRIX_KEY(0x03, 0x03, KEY_2)
|
|
MATRIX_KEY(0x03, 0x04, KEY_W)
|
|
MATRIX_KEY(0x03, 0x05, KEY_S)
|
|
MATRIX_KEY(0x03, 0x06, KEY_X)
|
|
MATRIX_KEY(0x03, 0x07, KEY_Z)
|
|
|
|
MATRIX_KEY(0x04, 0x00, KEY_LEFTCTRL)
|
|
|
|
MATRIX_KEY(0x05, 0x00, KEY_G)
|
|
MATRIX_KEY(0x05, 0x01, KEY_T)
|
|
MATRIX_KEY(0x05, 0x02, KEY_5)
|
|
MATRIX_KEY(0x05, 0x03, KEY_4)
|
|
MATRIX_KEY(0x05, 0x04, KEY_R)
|
|
MATRIX_KEY(0x05, 0x05, KEY_F)
|
|
MATRIX_KEY(0x05, 0x06, KEY_V)
|
|
MATRIX_KEY(0x05, 0x07, KEY_B)
|
|
|
|
MATRIX_KEY(0x06, 0x00, KEY_H)
|
|
MATRIX_KEY(0x06, 0x01, KEY_Y)
|
|
MATRIX_KEY(0x06, 0x02, KEY_6)
|
|
MATRIX_KEY(0x06, 0x03, KEY_7)
|
|
MATRIX_KEY(0x06, 0x04, KEY_U)
|
|
MATRIX_KEY(0x06, 0x05, KEY_J)
|
|
MATRIX_KEY(0x06, 0x06, KEY_M)
|
|
MATRIX_KEY(0x06, 0x07, KEY_N)
|
|
|
|
MATRIX_KEY(0x07, 0x01, KEY_F11)
|
|
MATRIX_KEY(0x07, 0x02, KEY_F10)
|
|
MATRIX_KEY(0x07, 0x03, KEY_9)
|
|
MATRIX_KEY(0x07, 0x04, KEY_O)
|
|
MATRIX_KEY(0x07, 0x05, KEY_L)
|
|
MATRIX_KEY(0x07, 0x06, KEY_DOT)
|
|
MATRIX_KEY(0x07, 0x07, KEY_DOWN)
|
|
|
|
MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
|
|
MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
|
|
|
|
MATRIX_KEY(0x09, 0x00, KEY_F7)
|
|
MATRIX_KEY(0x09, 0x01, KEY_F6)
|
|
MATRIX_KEY(0x09, 0x02, KEY_F5)
|
|
MATRIX_KEY(0x09, 0x03, KEY_8)
|
|
MATRIX_KEY(0x09, 0x04, KEY_I)
|
|
MATRIX_KEY(0x09, 0x05, KEY_K)
|
|
MATRIX_KEY(0x09, 0x06, KEY_COMMA)
|
|
|
|
MATRIX_KEY(0x0A, 0x00, KEY_F8)
|
|
MATRIX_KEY(0x0A, 0x01, KEY_F9)
|
|
MATRIX_KEY(0x0A, 0x02, KEY_BACKSLASH)
|
|
MATRIX_KEY(0x0A, 0x03, KEY_102ND)
|
|
MATRIX_KEY(0x0A, 0x04, KEY_COMPOSE)
|
|
MATRIX_KEY(0x0A, 0x05, KEY_LEFT)
|
|
|
|
MATRIX_KEY(0x0B, 0x00, KEY_RIGHTCTRL)
|
|
MATRIX_KEY(0x0B, 0x03, KEY_FN)
|
|
|
|
MATRIX_KEY(0x0C, 0x02, KEY_LEFTMETA)
|
|
|
|
MATRIX_KEY(0x0D, 0x00, KEY_MINUS)
|
|
MATRIX_KEY(0x0D, 0x02, KEY_0)
|
|
MATRIX_KEY(0x0D, 0x03, KEY_P)
|
|
MATRIX_KEY(0x0D, 0x04, KEY_LEFTBRACE)
|
|
MATRIX_KEY(0x0D, 0x05, KEY_SEMICOLON)
|
|
MATRIX_KEY(0x0D, 0x06, KEY_SLASH)
|
|
MATRIX_KEY(0x0D, 0x07, KEY_UP)
|
|
|
|
MATRIX_KEY(0x0E, 0x01, KEY_PRINT)
|
|
MATRIX_KEY(0x0E, 0x02, KEY_EQUAL)
|
|
MATRIX_KEY(0x0E, 0x03, KEY_BACKSPACE)
|
|
MATRIX_KEY(0x0E, 0x04, KEY_RIGHTBRACE)
|
|
MATRIX_KEY(0x0E, 0x06, KEY_APOSTROPHE)
|
|
MATRIX_KEY(0x0E, 0x07, KEY_ENTER)
|
|
|
|
MATRIX_KEY(0x0F, 0x02, KEY_DELETE)
|
|
MATRIX_KEY(0x0F, 0x03, KEY_PAGEUP)
|
|
MATRIX_KEY(0x0F, 0x04, KEY_INSERT)
|
|
MATRIX_KEY(0x0F, 0x05, KEY_F12)
|
|
MATRIX_KEY(0x0F, 0x06, KEY_PAGEDOWN)
|
|
MATRIX_KEY(0x0F, 0x07, KEY_RIGHT)
|
|
>;
|
|
};
|
|
|
|
sdmmc1: sdhci@78000000 {
|
|
status = "okay";
|
|
bus-width = <4>;
|
|
|
|
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
|
|
|
|
vmmc-supply = <&vdd_usd>;
|
|
vqmmc-supply = <&vddio_usd>;
|
|
};
|
|
|
|
sdmmc4: sdhci@78000600 {
|
|
status = "okay";
|
|
bus-width = <8>;
|
|
non-removable;
|
|
|
|
vmmc-supply = <&vcore_emmc>;
|
|
vqmmc-supply = <&vdd_1v8_vio>;
|
|
};
|
|
|
|
/* LEFT */
|
|
usb1: usb@7d000000 {
|
|
status = "okay";
|
|
dr_mode = "otg";
|
|
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
/* RIGHT */
|
|
usb3: usb@7d008000 {
|
|
status = "okay";
|
|
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
backlight: backlight {
|
|
compatible = "pwm-backlight";
|
|
|
|
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
|
|
pwms = <&pwm 0 4000000>;
|
|
|
|
brightness-levels = <1 35 70 105 140 175 210 255>;
|
|
default-brightness-level = <5>;
|
|
};
|
|
|
|
clk32k_in: clock-32k {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "ref-oscillator";
|
|
};
|
|
|
|
extcon-keys {
|
|
compatible = "gpio-keys";
|
|
|
|
switch-hall-sensor {
|
|
label = "Lid sensor";
|
|
gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_LOW>;
|
|
linux,code = <SW_LID>;
|
|
};
|
|
|
|
switch-rotation-lock {
|
|
label = "Rotation Lock";
|
|
gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>;
|
|
linux,code = <SW_ROTATE_LOCK>;
|
|
};
|
|
};
|
|
|
|
gpio-keys {
|
|
compatible = "gpio-keys";
|
|
|
|
key-power {
|
|
label = "Power";
|
|
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_ENTER>;
|
|
};
|
|
|
|
key-volume-down {
|
|
label = "Volume Down";
|
|
gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_DOWN>;
|
|
};
|
|
|
|
key-volume-up {
|
|
label = "Volume Up";
|
|
gpios = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_UP>;
|
|
};
|
|
|
|
key-windows-button {
|
|
label = "Windows Button";
|
|
gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_ENTER>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led-capslock {
|
|
label = "Capslock";
|
|
gpios = <&gpio TEGRA_GPIO(U, 2) GPIO_ACTIVE_HIGH>;
|
|
linux,default-trigger = "kbd-capslock";
|
|
default-state = "off";
|
|
};
|
|
};
|
|
|
|
panel: panel {
|
|
compatible = "simple-panel";
|
|
|
|
power-supply = <&vdd_pnl_reg>;
|
|
ddc-i2c-bus = <&gen2_i2c>;
|
|
|
|
backlight = <&backlight>;
|
|
};
|
|
|
|
vdd_edp_reg: regulator-edp {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vdd_edp";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
gpio = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
vcore_emmc: regulator-emmc {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vdd_emmc_core";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
vdd_pnl_reg: regulator-pnl {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vdd_panel";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
vdd_usd: regulator-usd {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vdd_usd";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
};
|