mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-16 09:54:35 +00:00
5d1aac358f
Updated PLL driver sequencing requires us to use udelay in the PLL driver as there is no poll bit to get the status of operations. tick-timer(mcu_timer0/main_timer0) setting up the clocks for itself is something that won't work as the PLL driver will be using udelay and PLLs are configured during clock probe which would end up in a recursive probe. tick-timer being used by K3 devices are configured by ROM and we really don't need to configure any of the clocks. Remove the clock dependency from R5 stage as we don't need to setup clocks for it. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
99 lines
2.1 KiB
Text
99 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
/ {
|
|
chosen {
|
|
tick-timer = &mcu_timer0;
|
|
};
|
|
|
|
aliases {
|
|
remoteproc0 = &sysctrler;
|
|
remoteproc1 = &a72_0;
|
|
};
|
|
|
|
a72_0: a72@0 {
|
|
compatible = "ti,am654-rproc";
|
|
reg = <0x0 0x00a90000 0x0 0x10>;
|
|
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
|
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
|
|
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
|
|
resets = <&k3_reset 202 0>;
|
|
clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
|
|
clock-names = "gtc", "core";
|
|
assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
|
|
assigned-clock-parents = <&k3_clks 61 3>;
|
|
assigned-clock-rates = <200000000>, <2000000000>;
|
|
ti,sci = <&sms>;
|
|
ti,sci-proc-id = <32>;
|
|
ti,sci-host-id = <10>;
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
dm_tifs: dm-tifs {
|
|
compatible = "ti,j721e-dm-sci";
|
|
ti,host-id = <3>;
|
|
ti,secure-host;
|
|
mbox-names = "rx", "tx";
|
|
mboxes= <&secure_proxy_mcu 21>,
|
|
<&secure_proxy_mcu 23>;
|
|
bootph-pre-ram;
|
|
};
|
|
};
|
|
|
|
&mcu_timer0 {
|
|
/delete-property/ clocks;
|
|
/delete-property/ clocks-names;
|
|
/delete-property/ assigned-clocks;
|
|
/delete-property/ assigned-clock-parents;
|
|
clock-frequency = <250000000>;
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&secure_proxy_sa3 {
|
|
bootph-pre-ram;
|
|
status = "okay";
|
|
};
|
|
|
|
&secure_proxy_mcu {
|
|
bootph-pre-ram;
|
|
status = "okay";
|
|
};
|
|
|
|
&cbass_mcu_wakeup {
|
|
sysctrler: sysctrler {
|
|
compatible = "ti,am654-system-controller";
|
|
mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
|
|
mbox-names = "tx", "rx", "boot_notify";
|
|
bootph-pre-ram;
|
|
};
|
|
};
|
|
|
|
&sms {
|
|
mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
|
|
mbox-names = "tx", "rx", "notify";
|
|
ti,host-id = <4>;
|
|
ti,secure-host;
|
|
};
|
|
|
|
&mcu_ringacc {
|
|
ti,sci = <&dm_tifs>;
|
|
};
|
|
|
|
&mcu_udmap {
|
|
ti,sci = <&dm_tifs>;
|
|
};
|
|
|
|
&ospi0 {
|
|
reg = <0x0 0x47040000 0x0 0x100>,
|
|
<0x0 0x50000000 0x0 0x8000000>;
|
|
};
|
|
|
|
&fss {
|
|
/* fss node has 64 bit address regions mapped to it and since the ospi
|
|
* nodes is being override, override the fss node ranges as well
|
|
*/
|
|
ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
|
|
<0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
|
|
};
|